Research On Imaging Technology Of Near-infrared Enhanced Photodetector With Super Large Array

The existing mature photoelectric imaging detection systems mainly include CCD and CMOS.In the field of near-infrared enhanced silicon photoelectric detection,CCD has better compatibility and imaging performance than CMOS technology and is widely used in various fields of the military and national economy.In order to solve the shortcomings of the current research on the imaging technology of large-area-array NIR-enhanced photodetectors in China,this thesis selects a 2048×256-area-array frame-shifted black silicon CCD as the image sensors and investigates the key technology of large-area-array NIR-enhanced CCDs in the process of building a NIR-enhanced CCD imaging system.In this thesis,there are many pins of super large array near-infrared enhanced CCD is large,and the photosensitive area,storage area,and horizontal area are all driven by multiphase clocks.Therefore,the key points of design include the generation of driving signals and the power supply structure of the whole system.At the same time,the CCD has multi-channel output,and there is non-uniformity between channels,so the elimination of non-uniformity also needs to be urgently considered.Because of the above technical difficulties,combined with the proposed design index of power consumption of not more than 30 W and frame rate of 175 Hz,the thesis determines the architecture of the whole system by using the idea of software and hardware collaborative design.At the hardware level,the thesis designs a CCD imaging platform,using Altera’s FPGA chip as the main control chip,the dual-channel AD9978 chip as the image frontend processing chip to complete the CCD output signal CDS,VGA,and AD conversion,the EL7457 chip suitable for driving high capacitive load as the driver chip,and Cameralink as the interface for data transmission.A multi-level distributed architecture power supply scheme is used in the power supply module with the idea of DC/DC+LDO.The design schematic and PCB layout of the corresponding modules are given to complete the hardware platform.At the software level,this thesis designs the control logic of the CCD imaging platform,using Verilog HDL for the logical description of each functional module.It mainly includes the clock scheme,the detector driver module that generates the drive pulse signal,the A/D chip configuration module that decreases the formation of the AD9978 data output,the bias chip configuration module that determines the size of the bias output,the image front-end module that re-integrates the 16-chip AD9978 output data cache,and the data output module.For the non-uniformity between channels,the two-point correction algorithm is chosen to correct the output image for non-uniformity after comparing several commonly used non-uniformity correction algorithms.Finally,the whole imaging system is tested and analyzed.The test results show that all the system voltages meet the power supply requirements,the driving pulse signal generated by the FPGA can drive the NIR-enhanced CCD correctly after level conversion,and the two-point correction algorithm achieves a good correction effect on the multichannel output CCD.The final power consumption of the whole system is 25.6 W and the frame rate can reach 173.5 fps,which provides a certain technical basis for the research of imaging technology of super large area array NIR-enhanced photodetector.