Hardware Design And Optimization Of Advanced Encryption Standard AES Algorithm

With the advent of the digital information age and the interconnection of all things,we enjoy the many conveniences brought by network technology to our lives,but also are always accompanied by the problems of information leakage,tampering and theft.Information security issues are particularly important,especially with the development of network communication technology and the continuous increase of the amount of transmitted data information,in order to make the data encryption algorithm better applied to the fields of biometrics,finance and wireless local area network communication,the throughput of encryption and decryption data is generally required to be tens of Gbit/s.Advanced Encryption Standard(AES)cryptographic technology has been widely used and researched in many fields at home and abroad because of its simple hardware structure,fast data encryption,and strong resistance to various attack methods.First,after in-depth research on the AES algorithm,this thesis uses the FPGA design method to implement the hardware system of the AES algorithm,and then proposes two optimization methods in terms of algorithm security.The first method is to solve the problem that the affine transformation period of the traditional S-box is small and the iterative output period has a short period.The new affine transformation pair(1C,DA)is used to reconstruct the S box,which improves the algebraic properties of the S box and improves the anti-attack ability of the S box.The second method is to improve the security of the key in the AES algorithm by improving the operation structure of the algorithm and reducing the correlation between the round keys,aiming at the security risks and low cracking difficulty of the traditional key expansion algorithm.Finally,the hardware system structure of the AES algorithm is optimized,and the Finite State Machine(FSM)design method is used to control the port connections shared by the resources of each sub-module,which greatly reduces the consumption of logic resources.Use software tools such as Quartus II and Modelsim to complete circuit synthesis and functional simulation,and compare and analyze the data of various indicators before and after optimization.The experimental results show that the total logic resource consumption before optimization is 10033 logic elements(Logic Element,LE),the maximum operating frequency of the system is 105.33 MHz,and the data throughput of the hardware system is 13.48 Gbit/s.After optimization,the total logic resource consumption of the hardware system is 6422 LEs,which is 36% less than before optimization.The maximum operating frequency of the system is slightly reduced to 81.81 MHz,and the system data throughput is 10.47 Gbit/s,but the overall speed-to-area ratio is improved.After optimization,the hardware system of AES algorithm changes from in terms of security,logic resource consumption,and speed-to-area ratio,they are all significantly better than before optimization,and the design basically meets expectations.