Research On RISC-V Vector Extended Communication Computing Technology

The RISC-V instruction set architecture is open source,free,flexible,and customizable,and it is one of the hot technologies in research and development.The RISC-V-based vector extension instruction set(RVV)supports variable-length vectors,which can flexibly realize efficient parallel processing of data,and has broad application prospects.Aiming at the application requirements of communication and signal processing,this thesis studies the vector extension acceleration technology based on RISC-V instruction set.The main work of the thesis is as follows:1)By studying the RISC-V instruction set,vector extension set and vector architecture,analyzing two different ways of implementing RISC-V vector extensions at present,combining their respective advantages and disadvantages,as well as the flexibility and scalability of application scenarios in the communication field,we propose an implementation architecture for RISC-V vector extensions,vector extensions for scalar processors in the form of coprocessor extensions,and SIMD streamline implementation.By adding vector register ports,two pipeline-conflict-free vector instructions are implemented simultaneously,supporting sequential firing,chaotic execution,and chaotic write back.And according to the workflow of vector instruction implementation,the microarchitecture of 256-bit vector processing unit is designed.The RTL design and connection of the module,functional verification and simulation,logic synthesis as well as implementation based on Vivado tools are completed to achieve a clock frequency of 100 Mhz.The performance of the vector processing unit is compared and analyzed by running 8*8,16*16,32*32 and 64*64 matrix operations,and compared with the scalar processor and the scalar processor based on the same coprocessor with custom instructions,it can be concluded that the acceleration ratio of the vector processing unit compared with the scalar processing unit is 33.7～48.4,and compared with the addition of The vector processing unit speedup ratio is in the range of 6.3 to 7.6 compared to adding custom matrix operation speedup instructions.2)For the requirements of communication algorithms such as matrix operations and FFT operations,an optimized implementation of matrix operations and FFT calculations based on RISCV vector expansion instructions is proposed to improve the parallelism of algorithm execution,reduce the number of moves of data in the middle of matrix operations between registers and memories by using vertical and horizontal processing in matrix operations,and improve the throughput rate.The combination of step storage instructions realizes data iteration for each level of FFT operation and reduces the number of instructions.According to the FFT algorithm rotation factor law,reading method,and implementation method,an implementation scheme based on RISC-V vector expansion for N-point FFT computation is proposed to reduce the overall code size and increase the algorithm execution rate.