Processor Core And SoC Design Based On RISC-V Instruction Set

With the development of the Internet of Things(IoT),the processor is an important core of the Internet of Things,and the requirements for its performance,area and power consumption are also increasing.The instruction set architecture(ISA)is the core of the processor and has a huge impact on its performance and microarchitecture.Currently,the vast majority of embedded processors are based on the ARM instruction set,but ARM instruction set licensing is expensive and complex.The RISC-V instruction set is gradually gaining attention in the embedded industry due to its advantages such as open source,simple instruction format,and support for custom extension instructions.Therefore,designing a RISC-V instruction set microprocessor that is suitable for embedded applications and easy to extend is of great significance.This thesis presents the design of a processor core that supports the RV64 IM instruction subset based on the RISC-V instruction set architecture.The processor core employs a five-stage pipeline technique and incorporates improvements on top of the classic five-stage pipeline:1)The processor core uses a branch prediction technique based on local history to improve the accuracy of branch prediction and reduce pipeline flushes caused by branch instructions.2)The processor core optimized the instruction fetch function by using a two-stage pipeline and a four-way set-associative Instruction Cache(I-Cache)module,coupled with instruction prefetch,to improve the fetch efficiency.3)Using a two-stage pipeline and a four-way set-associative non-blocking data cache(D-Cache)improved the efficiency of memory access instructions and increased the replacement speed of the D-Cache through a buffer queue.Based on this processor core,a SoC(System on Chip)platform is designed with memory,peripheral,and interrupt controller modules provided for the processor core.Furthermore,library functions are developed for each peripheral based on the SoC address space allocation,and a Bootloader program is written to facilitate program downloading on the SoC and ensure that the program is not lost after power-off.This thesis verified the functionality of the designed processor core and SoC platform through dynamic simulation and FPGA validation,and separately verified the performance optimization modules such as branch prediction union and Cache.After the test,the processor core and SoC platform function design is correct,branch prediction accuracy can reach above 91%.At a clock frequency of 50 MHz,the processor designed in this thesis achieves a Core Mark score of 2.89,outperforming low-end embedded processors such as ARM Cortex-M0.