Research On RISC-V Superscalar Out-of-order Processor

With the arrival of the intelligent era of internet of things,the advantages of Reduced Instruction Set Computing(RISC)become more and more prominent.As an open source RISC,RISC-V is more suitable for the current environment.In order to implement the instruction-level parallelism,the out-of-order superscalar architecture is widely used in high-performance CPU.Because of the complexity of scheduling instructions and branch prediction,Out-of-order superscalar architecture has always been a research hotspot.In this paper,the research of RISC-V out-of-order superscalar processor is carried out.(1)In order to solve the contradiction between high IPC(Instructions Per Cycle)and low delay in conventional issue architecture,withering logic is designed.The logic adds a FIFO queue named Sedimentation Tank.When the age of the instruction is greater than a threshold,the instruction will be written into the Sedimentation Tank from the issue queue.The instructions in the Sedimentation Tank can be unconditionally issued,and the threshold can be dynamically adjusted by the state of the Sedimentation Tank.At the same time,in order to further improve the performance of the issue logic,the instruction distribution logic,instruction request logic and wake-up logic are optimized.The evaluation results show that the designed can improve IPC by 25% compared with the issue logic with random select logic,the delay difference is only 6%,and the throughput is improved by 17%.Compared with the issue logic with conventional age-aware select logic,the circuit delay can be reduced by 34%,while the IPC difference is only 7%,and the throughput can be increased by 24%.(2)The problem of performance degradation of branch prediction is studied.It is found that performance degradation is caused by conflicts between sequences,failure to obtain oracle knowledge,memory blocking,statistical bias and other problems.The first three problems can be eliminated by getting rid of oracle knowledge,allocation policy and setting the saturation counter with appropriate number of states.However,the statistical bias can not be effectively solved in the algorithm level.To solve this problem,this paper designs a branch prediction assistant for RISC-V,mainly through correcting the statistical bias of the main branch predictor and the independent prediction of the loop containing unstable control flow,so as to reduce the statistical bias and further improve the accuracy of the branch prediction.The experimental results show that the performance of Gshare branch predictor and TAGE branch predictor is improved by 2.68% and 2.12% respectively.(3)Based on the optimized core,the RISC-V out-of-order superscalar processor So C is built,which can support 1-4 cores.The data transmission is based on Tile Link bus,and the peripherals such as SPI,UART,GPIO and debug module are mounted.At the same time,the Bluetooth is developed based on SPI interface,so that the So C can be used in the field of low-power wireless transmission.(4)Prototype verification,demonstration and performance test are carried out based on FPGA verification platform;synthesis and circuit delay evaluation are completed based on Design Compiler.The results show that the So C can boot Linux and execute related applications.It can also use Open OCD and GDB to debug the system.The Core Mark of the processor can reach up to 4.8 Core Mark/MHz,which is better than 3.77 Core Mark/MHz of BOOMv2.To sum up,this paper studies the high throughput out-of-order issue logic in steady state,and the performance degradation in branch prediction.Based on the above research,the RISC-V Out-of-Order superscalar processor So C is built.Finally,the FPGA prototype verification and system demonstration are carried out.The experimental results show that the Core Mark performance is better than that of BOOMv2.