Research On Layer-aware Models And Data Placement In 3D NAND-based Solid State Drives

The stacking architecture of 3D NAND flash memory offers a promising solution for increasing flash capacity and reducing the per-unit bit price.However,this architecture introduces new reliability challenges,particularly retention errors caused by charge leakage,which are the main reason for read-retry in high-density flash memory.This paper focuses on the issue of retention errors in 3D NAND flash memory and conducts research and exploration from the following perspectives.(1)The flash block serves as the basic unit for complete program and erase operations in flash memory.This paper proposes an empirical mathematical model based on the granularity of flash blocks to estimate the bit errors caused by retention errors.The model considers the interference between layers within the flash block,early retention loss,program/erase cycle,and data retention time of 3D NAND flash memory.The reliability and accuracy of the mathematical model are verified through case studies involving four mainstream commercial 3D NAND flash memory products.(2)In 3D NAND flash memory,the performance variation caused by the manufacturing process leads to significantly different raw bit error rates(RBER)between flash memory cells in different layers of the flash block.This paper studies the factors of error rate variation between layers in 3D NAND flash memory,improves the retention error model based on the commonality in error rate changes,and classifies different performance layers according to the ECC(Error Correction Codes)time overhead between different flash layers.(3)Building upon the performance differences and classification of different layers in 3D NAND flash memory,as well as the characteristics of unbalanced I/O data access,this paper designs a data placement mechanism to enhance the read performance of 3D NAND flash memory by considering data hotness and inter-layer performance differences.The proposed mechanism strategically places frequently accessed data on profitable layers and infrequently accessed data on negative profit layers.(4)Using real disk-based workloads for experiments,the results show that the proposed mechanism effectively utilizes the inter-layer performance difference feature.Compared with existing data placement mechanisms for 3D NAND flash memory,the proposed mechanism can reduce the average read latency and average I/O latency of solid-state drives by 12.9% and 6.2%,respectively.