Research On Single Event Upset Effect Of D Flip-flop Under Nanotechnology

With the development of technology,memory devices represented by flip-flops are becoming more and more sensitive to single event upset(SEU).The lower supply voltage and reduced node capacitance reduce the critical charge that causes SEU.With the shrinking of the process size and the close arrangement of transistors,single-event-effect can lead to charge sharing at multiple nodes,which poses a severe challenge to the radiation-hardened of the flip-flop.This article takes nano-process D flip-flop as the main research object,combined with heavy ion experiments and simulation experiments,the upset-resistant performance and radiation-hardened scheme of the DICE structure D flip-flop are analyzed from the perspective of circuit,layout,and well-process.The single event characteristics of the FinFET process are studied and compared with the planar process.The main research work and results are as follows:(1)The influence of the different connection modes between the master and slave stages on the flip-flop upset.Through 40nm DFF test chip heavy ion experiment,it is found that the upset cross section of the DFF is significantly different when the DFF uses different master-slave connection modes.The SEU sensitivity of the two connection modes of transmission gate and C~2MOS in the flip-flop is compared,and it is pointed out that the traditional transmission gate structure has a reverse conduction problem,which will deteriorate the flip-flop resistance of the main stage of the flip-flop.An optimization method is proposed for the traditional transmission gate structure.SPICE simulation and TCAD simulation results verify the effectiveness of the method.(2)The influence of different layouts and well processes on flip-flop upset.Through28nm DFF test chip heavy ion experiment,it is found that once the flip-flop uses different PMOS and NMOS correspondences,and the response to single particles is different,and it is related to the storage state.It is demonstrated through TCAD simulation that different transistor arrangement orders will also affect the upset sensitivity,and the adjacent placing of larger-size sensitive transistors will worsen the effect of single event.For the upset caused by NMOS-hit-induced PMOS charge sharing,and the flipping caused by PMOS-hit-induced PMOS-PMOS charge sharing in the N well,adding the deep N+well has a certain inhibitory effect.(3)Comparison of single-event characteristics of FinFET technology and planar bulk technology flip-flops.Through the comparison of FinFET process and planar bulk process heavy ion experiments,it is found that the FinFET process has a weaker charge sharing effect and stronger resistance to single event upset.The upset cross section of the ordinary D flip-flop is equivalent to the cross section of the 28nm planar bulk silicon process DICE-hardened flip-flop.Through the TCAD simulation experiment,it is proved that the FinFET process has a weaker charge sharing effect and a higher D flip-flop upset threshold.This article focuses on the single event upset effect of nano-process D flip-flops,and conducts research on upset mechanism and radiation-hardened methods.The conclusions obtained have certain reference value and guiding significance for the design of radiation-hardened integrated circuits.