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Implementation Of High Speed Protocal Conversion And Encryption System Based On FPGA

Posted on:2021-04-04Degree:MasterType:Thesis
Country:ChinaCandidate:J M YangFull Text:PDF
GTID:2568306104470574Subject:Electronic Science and Technology
Abstract/Summary:PDF Full Text Request
In today’s society,there are many different communication protocols in various communication occasions.With the increase of communication protocol types,data interaction and protocol conversion between different communication protocols have gradually become a research hotspot.With the development of multi-channel,large data volume,high data transmission rate and high-speed real-time processing technology,the function and performance requirements of data processing between different communication protocols are gradually improved.Data processing between different communication protocols requires special processing equipment.This paper aims to design a high-speed protocol conversion system(high speed protocol conversion and data encryption processing based on FPGA)for satellite ground detection based on FPGA.Firstly,FPGA is selected as the core of data processing according to the function and performance index of high-speed protocol conversion system proposed by a research institute,The overall design of the high-speed protocol conversion system is carried out,and the corresponding implementation scheme is formulated.The Gigabit Ethernet data transmission,high-speed serial GTX transmission and other technologies in the system are studied.Based on the overall design scheme,high-speed protocol conversion principle and relevant technical demonstration,a set of FPGA based satellite is designed according to the FPGA hardware development and FPGA logic design flow The high-speed protocol conversion system of ground detection is implemented.The system receives Ethernet frame data through 88e1111 PHY chip,converts the data into special link frame and encrypts it in FPGA,and completes the high-speed serial transmission and protocol conversion between chips and devices.At the same time,the configuration system of the upper computer is designed and implemented,which improves the flexibility of the system.The design content of this paper is mainly divided into two parts: hardware design and logic design.The hardware part mainly includes the principle design and analysis of the core part,the principle and design of the peripheral circuit,etc.The logic design part mainly includes UDP protocol frame data receiving,FPGA chip communication module,high-speed protocol conversion and encryption and decryption module and GTX based high-speed serial data transmission module.Finally,the production of the prototype and products is completed,and the usability of the equipment is verified through the test of the function and performance of the equipment by Party A.
Keywords/Search Tags:ground inspection, FPGA, high speed protocol conversion, UDP, real time encryption and decryption, inter chip communication
PDF Full Text Request
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