Research On Related Problems Of LDPC Code Decoder Design Based On CUDA Heterogeneous Computing

With the advancement of the era of big data and the advent of the 5G era,the field of communications and data storage have become more and more concerned in recent years.With the continuous promotion of market demand,channel-coding technology has gained considerable attention in both fields development.The LDPC（Low-Density Parity-Check）code in channel coding has been widely used in the communication field and error control of flash memory storage due to its excellent error correction performance close to Shannon’s limit.The graphics processing unit has a large number of parallel mechanisms and has been widely used in high-performance computing.CUDA is an extension of C language developed by NVIDIA for parallel computing.In the research process of LDPC codes,compared with the long process on FPGA,the powerful computing power and high flexibility of GPU have great help in the need to test the decoding performance of LDPC codes in large quantities.Using this CUDA heterogeneous computing platform to achieve the convenience of the LDPC decoder,without changing the general code structure,only changing the LDPC code reference matrix,we can make a very fast test of the LDPC code decoding performance.It is more convenient,flexible and fast than the implementation process of the same decoder on the FPGA development board.In the course of carrying out the project,this platform does provide a great convenience for finding the suitable LDPC code construction process that meets the performance requirements.This paper completed the realization of GPU-based high-throughput LDPC decoder.By applying a novel message update scheme and reducing the consumption of shared memory,a minimum-sum algorithm decoder based on TPMP and layered-MPD is designed,as well as gradient descent based on Bit Flipping Hard decision decoder for bit flipping and probabilistic gradient descent bit flipping.At the same time,the802.11n standard（1944,972）LDPC code and the 4KB code length QC-LDPC code used in flash memory were studied.（1944,972）The TPMP decoder implemented on the single-chip Ge Force GTX1080 Ti GPU with LDPC codes can reach a throughput of 4.77 Gb/s,while the layered-MPD can reach 3.67 Gb/s.The throughput of the GPU-based decoder is comparable to the decoder implementation on the FPGA development board.For the QC-LDPC code with a length of 4KB,the NMS algorithm decoder of the layered-MPD process has no error when the frame error rate drops to the order of 10^-8 under the conditions of the AWGN channel.the maximum iteration number of 20 An error flat-bottom phenomenon occurs;the decoder of the PGDBF hard decoding algorithm of the TPMP process is compared with the Green mode scheme proposed by SMI,and the decoding performance is slightly better under the same code length.This code has good practicality in the application of new generation flash memory error correction.