Study On Current Sharing Of Paralleled SiC MOSFET Based On Response Surface Analysis And Particle Swarm Optimization

Semiconductor power devices are the essential components of electric vehicle energy inverter,which obviously affect vehicle dynamic quality and energy economy.The third generation of semiconductor power devices based on wide bandgap(WBG)SiC materials have the advantages of low on-resistance,high operating voltage,high switching frequency and high operating temperature,which can significantly improve the efficiency and power density of power electronics system,simplify hart sink and reduce system volume,thence it can effectively assist the development of high-performance electric vehicle drive system.At present,due to SiC substrate defects and SiC MOSFET processes constraints,single MOSFET chip’s current level is limited to less than 100A.In order to meet the high power usage demands of high performance electric vehicle,it is a mainstream solution to pack multiple SiC MOSFET chips into a power module in parallel.However,current imbalance caused by asymmetric DBC layout will lead to over voltage,over current,high temperature even damage of MOSFET and SiC power module.Therefore,studying current sharing influence factors and optimization methods can improve performance and reliability of SiC power module.Aiming at research requirements of excellent performance multi-chip SiC power module,this thesis systematically analyzes factors affecting current sharing,tries to put forward optimization schemes to minimize current difference and improve current sharing effect in parallel chips.In the first place,influencing factors of current sharing are analyzed.A parallel three-chip circuit model is established,and influence of parasitic inductance generated by package on current sharing is systematically analyzed by combining theory and simulation when chips’ gate is Kelvin-source connection and common-source connection.The mechanism of source inductance on current balance under two connection modes is revealed,which lays a foundation for the subsequent optimization.Afterwards,calculation method of parasitic inductance is studied.Based on a designed SiC power module,three parallel branches equivalent source parasitic inductance are calculated while considering the coupling effect of DBC common inductance.And current simulation shows the difference of equivalent source inductance will cause serious current imbalance.Influence of bonding wire and DBC design parameters on parasitic inductance are analyzed by response surface method(RSM),in the meanwhile the calculation model of parasitic inductance is obtained.Secondly,two optimization schemes and a new index are proposed to balance parallel branches’parasitic inductance and current sharing.In the light of calculation model of equivalent source parasitic inductance,some optimization directions is theoretically analyzed,then a new index is proposed,which can optimize average value and difference of source parasitic inductance simultaneously.In addition to only adjusting the length of bond wire,this thesis proposes a method to obtain better balance inductance,which simultaneously optimizes the length of bond wires and the shape of source DBC trace.Response surface method and particle swarm optimization algorithm are used to acquire the optimal design of two optimization schemes,hereafter,parasitic inductance balance effect is compared.Ultimately,effect of current sharing optimization is verified.Ltspice double-pulse simulation is used to compare current sharing of two optimal designs.Three experimental samples are designed and manufactured,and parasitic inductance are measured by LCR Analyzer to verify the proposed index and optimization scheme have better parasitic inductance and current sharing balance effect.