Planar Interconnection Packaging Technology Of Power Module And Research On Its Parasitic Inductance And Switching Characteristics

The traditional packaging structure using wire bonding technology introduces significant parasitic inductance within the power module.Under high switch frequency and high power density operating conditions,this can cause a series of issues,such as voltage overshoot,voltage and current oscillation,and increased switching losses,seriously affecting the switching characteristics of the power module.Currently,with the rapid evolution of power semiconductor technology,power devices using existing packaging forms have gradually become unable to meet the future development needs of power electronic systems in terms of electrical performance.There is an urgent need to develop a new generation of low-inductance power module packaging technology.In response to the above issues,this article summarizes the current domestic and foreign research status of advanced low-inductance packaging solutions for power devices.Then,a power module planar interconnect packaging technology is proposed to reduce parasitic inductance,improve switching performance,and reduce packaging process complexity while increasing batch production efficiency.The article takes the IGBT half-bridge topology circuit as the research object and conducts electrical simulation analysis,sample packaging preparation,and electrical characteristic testing.The main research content and analysis results are as follows:In terms of device simulation,this paper extracts the local and overall parasitic inductance of the power module using finite element software and builds a double-pulse simulation test circuit to compare and evaluate the static and dynamic electrical performance of the planar interconnection and wire bonding interconnection structures under the same conditions.The simulation results show that when planar interconnection packaging technology is used to replace wire bonding technology,the overall commutation loop in the power module can be reduced by 21%,and the average current-carrying capacity in the interconnection area is greatly improved.In addition,thanks to the low parasitic inductance characteristics of the planar interconnection structure,the power module can reduce the voltage overshoot by 4.68% and the loss by 34.8% during the turn-off process.The voltage and current oscillation phenomenon is effectively suppressed,and the dynamic switching performance of the module is significantly improved.Next,in terms of device fabrication,the paper focuses on introducing the planar interconnection packaging method for the power module,including power chip reflow soldering,internal insulation sealing,interconnection circuit design and fabrication,and terminal soldering.In addition,the quality issues of magnetron sputtering and vacuum injection molding are analyzed and discussed.The optimization scheme to improve the bond strength between sputtering films and reduce the resin porosity is explored theoretically and practically,providing reference for further improving the planar interconnection structure fabrication process and increasing packaging production efficiency.Finally,in terms of device testing,the paper constructs a second-order RLC series circuit model for the IGBT power module and uses vector network analysis and impedance analysis to perform two-port and single-port tests,respectively.The local and overall parasitic inductance levels of the power module are obtained by synthesizing the Sparameter and Z-parameter curves measured.The experimental results show that the planar interconnection packaging module has low overall parasitic inductance,which is basically consistent with the simulation results.The factors and causes of errors in the test results are discussed,and the possible defects in the test circuit are analyzed based on the characteristic rules of the obtained results.