Sparse Convolutional Neural Network Accelerator Design

In the recent years,with the development of deep learning theory and the growth of hardware computing capacity,convolutional neural networks have been widely used in many fields.However,the increments of parameters and computation of convolutional neural networks make it more difficult to be deployed on terminal devices,such as embedded,mobile devices and so on.Network pruning can effectively reduce the amount of parameters and computation of the network,but it also causes irregularity in network connections,which makes existing accelerators hard to harness sparsity for acceleration.In order to solve the above problems,this paper designs a sparse convolutional neural accelerator that can make use of the sparsity of network.The main work of the thesis is as follows:(1)In view of the characteristics of less non-zero weight data in the network after pruning,this paper models the sparse convolutional neural network,and analyzes the amount of data access amount and median storage under different data replacement strategies.Combined with output channel parallelism,a parallel Input Feature Slide First(IFFS)data stream of output channels is proposed.Compared with other data streams,the proposed data stream has less the amount of data access and median storage.Then,in view of the irregularity of non-zero weights after pruning,this paper designs a sparse weight encoding method to compress and encode the weight data,introduces the position information of column offset and index record weight,and only retains non-zero weight data.Based on the proposed coding method,the overall sparse weight compression ratio of convolution layers and fully connected layers of VGG-16 achieves6.3,which effectively reduces the storage space occupation of weight data.(2)Based on the parallel output channel IFFS data stream and sparse weight coding method,this paper designs a sparse convolutional neural network accelerator.The accelerator can use the weight and feature sparsity brought by pruning and Re LU activation function to skip zero-value operations.The non-zero detection module of the accelerator dynamically detects the input features and filters out the non-zero features.Then they are transmitted to the sparse processing unit group to read the non-zero weights required for calculation.(3)Based on the Xilinx ZCU104 platform,a sparse convolutional neural network accelerator is implemented,and the design space is explored to determine the optimal configuration of the sparse processing unit group.Experimental results show that the designed accelerator has an effective throughput of 140.7 GOPs for VGG-16,a power consumption of 5.067 W,and an energy efficiency of 25.1 GOPs/W.Compared with the existing convolutional neural network accelerators,the power consumption is reduced by 1.6-4.6 times.The energy efficiency is improved by 1.1～7.6 times.