Research And Design Of A 14 Bit Successive Approximation Register ADC Based On Self-Calibration Technique

Analog to Digital Converter(ADC)is a bridge between analog signals and digital signals.With the advent of Internet of Everything,ADC is widely used in the Internet of Things,wearable medical devices and consumer electronics and etc.At the same time,the demand for high-performance ADC is becoming more and more urgent.SAR ADC have the advantages of low power consumption,medium to high accuracy,medium to high speed,and benefit from the development of CMOS manufacturing processes,making them a hot research topic for universities,research institutes and companies.This thesis investigates and designs a 14-bit fully differential SAR ADC with self-calibration technique at a sampling frequency of 200KSps and a reference voltage of 4.096V.In this thesis,the sample-and-hold circuit based on gate-voltage bootstrap switch structure is used to reduce the impact of input signal on its on-resistance,which can effectively improve the linearity of the sample-and-hold circuit;The high precision comparator combines the advantages of the static pre-amplifier and the dynamic latch.The self-calibration technique and the output offset storage technique are used to calibrate the offset of the comparator.The calibrated comparator can recognize the voltage of 0.5LSB;The Capacitor array of fully differential Digital to Analog Converter(DAC)is a segmented structure,in which the MSB array is 10-bit and the LSB array is 4-bit,and the successive approximation method of first comparing and then setting is used.On the premise of avoiding the parasitic influence of the bridge capacitor as much as possible,the required number of unit capacitors is saved,the total capacitance value of the structure is 1048 unit capacitors,and compared with the traditional charge-type DAC structure,the area is saved by 93.6%;With regard to the influence of non-ideal factors such as capacitor mismatch,the self-calibration technology is used to calibrate the comparator offset and the high-three bit capacitor mismatch.The error code is obtained in the calibration stage,and the error voltage is compensated by the calibration DAC in the normal conversion stage,so as to realize the calibration function.In this thesis,the whole circuit of SAR ADC is designed and simulated by Cadence in Eastern 0.18μm CMOS process,and the simulation results are as follows:when the input frequency is 5.078125KHz,the amplitude of sine wave is 0～4.096V,the effective number of bits(ENOB)is 13.3477bit,the spurious free dynamic range(SFDR)is 93.7697dB and the signal to noise and distortion ratio(SNDR)is 82.1219dB.