| Convolution Neural Network(CNN)is the most successful artificial Neural Network,which applied in computer vision,image recognition and classification area.Highly developed in recent decades makes the application of convolutional neural network abroad around us.Actually,the structure of a high-performance neural network is huge,a great number of calculations is required for inference.While the calculation to train a high-performance convolutional neural network is dozens of times or more.In line with state of the technology,it is impossible that one net be adapter in all fields.Different scenarios need a specific neural network structures and related data sets.Computing power requirement and data sets for training are the keys to obtain a high performance convolutional neural network.Improve the computing power is always the focus issue of enterprise engineers and researchers.It is difficult to dramatically improve the performance of traditional CPU,unless a disruptive technological breakthrough,such as a quantum computer,which is unlikely to happen in the short term.Heterogeneous computing is the mainstream idea at present.This method is to make full use of the parallelism of computing to realize the computing part on the external hardware,and then through the bus or other forms of integration,the hardware part as a traditional CPU’s external device,so as to achieve the purpose of improving the computing power.Realization of heterogeneous accelerator in three directions: Graphics Process Unit(GPU),Field Program Gate Array(FPGA),and Application Specific Integrated Circuit(ASIC).As a programmable logic device,FPGA is favored by researchers because of its flexibility,reconfiguration and low cost.FPGA can not only be used as the initial research and test,but also can directly replace ASIC as a product release in some scenarios,which can greatly reduce the product cycle.For exploring the heterogeneous acceleration of FPGA.Here implemented NVDLA,which is an open source hardware inference framework,work through a heterogeneous acceleration interface scheme based on FPGA acceleration this paper proposed.With a scale of 8x8 multiplicative accumulator is implemented on FPGA with a frequency of 125 Mhz and computing capacity of 16 GOPs.Compared with CPU(I7-10510U),the calculation efficiency on Le Net5 is increased by about 21.9%.Effectiveness of the way is proved by experiment.Further more,here proposed a method of heterogeneous accelerator which based on operator for on-chip training on FPGA,based on the achievement of the interface scheme as previously mentioned.The key characteristic is modularization,which has excellent universality and does not need to consider different types of net structures.Different neural net built in the system software side,which is easy to update and iterate.This research focus on back propagation in convolution layer.Here designed a module,a 32-bit floating point reverse calculation which contains a scale of 8x8 multiplication matrix and an 8 input 3pipeline adder.Its capacity up to 14.22 GFOPs.Experimental analysis proves that the computational capability of this scheme is better than that of the CPU processor in the scenario of large computation. |
