Design And Implementation Of Real-time Overlay Error Measurement System Based On FPGA

As the chip manufacturing process continues to shrink and the number of circuit layers continues to increase,the overlay-related indicators of the advanced node manufacturing process are more stringent,and how to measure the overlay error accurately and quickly becomes more important.Overlay error measurement is a key step in overlay,and shortening the measurement time will greatly improve overlay efficiency,thereby improving chip productivity and yield.In order to solve this problem,this paper takes the digital image processing technology as the guide,designs and implements the algorithm for the overlay error measurement,which greatly shortens the time required for the measurement.The main work of this paper is as follows:1.Design and implement an overlay error measurement algorithm.This algorithm involves the steps of image threshold acquisition,template matching,correlation coefficient calculation and sub-pixel error calculation.It is based on the design idea of parallel pipeline,and fully considers the feasibility of hardware implementation.While ensuring the rational use of hardware resources,the measurement accuracy of nanometer-level overlay error is achieved.2.Design and implement an eight-direction Sobel adaptive threshold edge detection algorithm.Before performing the overlay error measurement algorithm,the image is filtered and preprocessed by edge detection to avoid the misidentification of overlay marks caused by image noise or false edges.For the form of overlay marks,the traditional two-direction Sobel operator is extended to eight directions,which can effectively detect overlay marks of multiple angles,while avoiding the phenomenon of unclear identification of overlay marks in non-X and Y directions.Median filtering is performed using local adaptive threshold,and the threshold is dynamically adjusted adaptively according to the local gray value of the image,which avoids the blurring of overlay marks caused by setting the global threshold.3.Combined with software model,hardware board and experimental machine,the algorithm is implemented and verified.The algorithm model is built through the software,and the feasibility simulation verification of the demand realization of the overlay error measurement algorithm is carried out;Algorithm coding and simulation based on FPGA board are compared with the software results to verify the correctness of the hardware implementation;The experiment was carried out using the overlay error measuring machine,and the error and time-consuming results fed back by the host computer were compared with the traditional equipment.On the premise of ensuring the measurement accuracy,the timeconsuming was shortened from 82.23 ms to 11.21 ms,saving 86.37% time,thus verifying the effectiveness of the system.The validity of the overlay error measurement algorithm and the feasibility of the system are verified by means of simulation verification and machine experiments.Compared with the traditional system,this system has obvious measurement speed-up effect,and has important reference value for overlay error measurement and overlay alignment.