Design Of High Speed Data Acquisition Process Based On NoC

With the requirement of high speed and high real-time signal acquisition in the field of electronic information,the demand of higher signal sampling rate is proposed.The lack of extensibility and complexity of clock tree in So C architecture form is prominent,which is caused by the increase of IP core and the expansion of resources.The clock independence between the network-on-chip routers enables the computing units between the routers to be separated from each other,which facilitates the topology of the system.The fact that the clocks between the on-chip network routers are independent enables the computing units between the routers to be separated from each other.This feature makes the topology of the system convenient and generality improved.Therefore,referring to the technical advantages of NoC,this paper designs a data acquisition system based on NoC architecture to overcome the disadvantages of So C sampling.For the application of NoC in data acquisition system.In the NoC topology form of the traditional 2D matrix Mesh structure,there is a problem that the data acquisition resource nodes cannot be completely symmetrical and will be evenly distributed.This leads to inconsistent path planning in the process of data transmission,so that the data in different directions can not be unified in the transmission design.In order to solve this problem,a rhombic NoC topology is designed in this paper.The routing node of this structure is mainly divided into two parts: master and slave,so that each slave node can evenly allocate resources.The problem of data transmission path is also unified.The clock sources of each route in NoC are separated from each other in the form of global asynchronous and local synchronous.Referring to the synchronization mode of White Rabbit-Precise Time Protocol,this paper designs the PTP synchronization protocol and realizes the first time synchronization process of master-slave nodes.The second phase synchronization is carried out by using Digital Dual Mixer Time Difference technology.Therefore,The problem of time synchronization between asynchronous routing nodes is solved..To overcome the limitation of sampling rate for a single ADC,the sampling rate of the system is further improved.The principle of time interleaving sampling is used for multi ADC expansion.This paper realizes the verification that the sampling rate of single ADC is 500 Msps and the sampling rate of two interleaved ADC is 1Gsps.In addition,the difference between interleaved sampling and monolithic sampling is also compared.In the case of low data transmission speed in the process of high-speed data acquisition,the performance requirements of high-speed and high real-time can not be achieved.Therefore,in terms of data transmission interface,it is designed to be compatible with pcie2.0 protocol.The PCIe interface with the highest 4GB/s transmission rate is realized.In conclusion,this paper designs a diamond NoC architecture with five node structure based on Xilinx K7 series FPGA.The design of data packet and the design of transmission function with transmission bandwidth of 200 MB / s are realized.It can meet the requirements of 1Gsps(128MB / s)sampling rate.In terms of master-slave synchronization,the PTP synchronization process is verified,and the accurate phase difference of 100 MHz clock between master and slave is calculated.The sampling Party of time interleaving verifies that the interleaving of two ADCs realizes the sampling index of 1gsps.The maximum transmission rate of PCIe interface is 4GB/s.