Design Of A Wideband Low Phase Noise And Low Spurious Fractional-n Frequency Synthesizer

The frequency synthesizer is an important part of the modern electronic system,which often provides low phase noise,low spurious and high resolution local oscillator signal for the radio frequency transceiver system in the field of wireless communications.With the rapid development of the wireless communication technology,communication standards in different fields such as mobile communication,satellite navigation,and wireless local area network have gradually emerged.In order to meet the rich needs of people’s life,it is necessary to integrate different communication standards into a radio frequency transceiver system.In this paper,a fractional-N frequency synthesizer supporting multiple communication standards is studied.Finally,a wideband,low phase noise and low spurious Σ-Δ fractional-N frequency synthesizer which is based on charge pump phase-locked loop is designed.Based on the edge-triggered structure,a true single-phase clock trigger is adopted in the phase-frequency detector with high working speed and no dead zone.A dynamic current compensation technology is used in the charge pump,of which the output voltage range can reach0.2～1.0V,and the current variation range is 81～123μA.The frequency synthesizer realizes wideband output through three voltage-controlled oscillators and programmable frequency division links,and the frequency range of the voltage-controlled oscillator reaches 6～12GHz.An adaptive body-biasing technique is introduced into the voltage-controlled oscillator to reduce the effect of PVT variation,of which the phase noise is lower than-109 d Bc/Hz@1MHz.A retiming unit is taken in the programmable frequency divider to synchronize the output,which improves the phase noise of the output signal by 3.54 d B when the carrier frequency offset is 100 k Hz.In the automatic frequency calibration module,a structure that directly counts the voltage-controlled oscillator and a successive approximation algorithm based on the binary method are used to shorten the calibration time.The simulation results show that the coarse frequency tuning time is only 4.6μs.The HK-EFM and SP-EFM structures are adopted in the Σ-Δ modulator,which make the output sequence length no longer change with the variation of decimal input value,and the notch filter structure introduced reduces the high-frequency quantization noise.Finally,the fractional-N frequency synthesizer is designed in 65 nm CMOS technology,and the layout area of the circuit is 1910μm×904μm.The post-simulation results show that the locking time of the frequency synthesizer is less than 40μs,and the quadrature output frequency range is0.2～6GHz.When the output frequency of the frequency synthesizer is 3.7625 GHz,the phase noise is-93.2d Bc/Hz@100k Hz and-113.59 d Bc/Hz@1MHz,the reference spur is-67 d Bc and the fractional spur is-76 d Bc.The overall power dissipation of the circuit is 91 m W at a supply voltage of 1.2V.