Research And Design Of 12-bit High Speed SAR ADC

The successive approximation register(SAR)ADC has the advantages of low power consumption,small area,simple structure and so on,and it is widely used in medical wearable devices,aerospace,industrial measurement and other fields in which high sampling rate is not required.In recent years,with the improvement of process technology and design ability,SAR ADC has become the research hotspot in high-speed ADC.In this paper,the main functional modules of medium-precision and high-speed SAR ADC,such as sample and hold circuit,digital to analog converter(DAC),comparator and multiphase clock circuit are studied,and a 12 bit high-speed SAR ADC with sampling rate of 80 MS/s is designed.The segmented DAC with redundant bits is used to improve the conversion speed and reduce the nonlinear error of the high-segment capacitor array.In the sample-and-hold circuit,gate voltage bootstrap switch and bottom plate sampling technology are used to improve the accuracy.The comparator adopts dynamic pre-amplification stage regenerative comparator,which reduces power consumption and improves speed.Since the clock frequency of the traditional multiphase clock generation circuit is easily affected by the changes of process,voltage and temperature,the digital calibration method is adopted to improve the above circuit,which improves the stability of the clock signal frequency.The circuit schematic and layout are designed in 40 nm CMOS process.The core area of the layout is 540 μm×70 μm.The simulation results show that the power consumption of ADC is 4.06 mW,the sampling rate can reach 80 MS/s,the spurious-free dynamic range(SFDR)is 77.9 dB,the signal-to-noise distortion ratio(SNDR)is 71.2 dB,the figure of merit(FOM)is 17.5 fJ/conversionstep,and the effective digit(ENOB)is 11.5 bit.