Research And Design Of 16Gbps＿SerDes＿TX Circuit Based On 28nm Process

With the rise of big data and the rapid development of information technology,the demand for bus bandwidth for data transmission is increasing.The development of parallel transmission technology has been hampered by a series of problems such as difficult timing synchronization,serious signal offset,weak interference immunity,and high design complexity.Compared to parallel transmission technology,serial transmission technology,represented by the SerDes(Serializer,De-serializer)system,is now widely used in embedded high-speed transmission because of its low pin count,high scalability,and point-to-point connection and the ability to provide higher bandwidth than parallel transmission.The SerDes is a complex digital-analog hybrid system,including semi-custom,full custom,and pure analog circuits.At the same time,the processed signal rate is usually up to Gbps or more,which is tens of times the main frequency of general microprocessors,thus a series of high-speed signal integrity problems,such as dielectric loss,crosstalk,inter-code interference,etc.,have been faced,making the SerDes design more difficult.This thesis investigates and designs SerDes transmitter circuits for high-speed signal integrity issues in the context of the need for high-speed and high-quality data transmission.First,for the high-speed clock(16 GHz)to properly implement the dichroic function,the C2MOS D flip-flop is designed to avoid jitter caused by clock overlap,which affects the clock quality.Secondly,a re-timing circuit is added after each MUX circuit to have a good output waveform for the serializer circuit,which reduces output burr and clock-induced data jitter.Finally,to make the signal better adapt to different channel attenuation,a programmable current-mode logic driver is used at the output to make the pre-emphasis gain adjustable from 0 to 10.46 dB.In this thesis,based on the UMC 28 nm standard CMOS process,the pre-simulation verification of the designed modules was performed using the Cadence tool,and the layout drawing and post-simulation verification of the single-channel SerDes transmitter was completed with an overall circuit layout area of 226 μm × 100 μm.The post-simulation results show that the designed SerDes transmitter can achieve a maximum data transfer rate of 16 Gbps with a differential output eye diagram data jitter of 0.059 UI(Unit Interval)and an eye diagram width of 0.94 UI without pre-emphasis at a supply voltage of 0.855 V,ss process angle and 125℃,which meets the protocol requirements.