Timing Recovery Module Implementation Based On FPGA And Experimental Verification In High-Speed Space QPSK Coherent Optical Communication Receivers

Space laser communication has the advantages of high speed,large bandwidth and strong anti-electromagnetic interference ability,and becomes one of the research hotspots in space communication field.Digital coherent optical communication technology based on Digital Signal Processing(DSP)has become one of the key technologies in the field of space optical communication due to its high sensitivity,large channel capacity,high spectral efficiency and the ability to use DSP algorithm to compensate various channel damages.However,there are few real-time DSP algorithms for spatial optical communication,so it is valuable to design and implement a real-time DSP algorithm for spatial optical communication with low complexity and easy implementation by FPGA based on the traditional DSP algorithm for optical fiber channel.This paper mainly focuses on the design and implementation of real-time DSP algorithm for digital coherent receiver of QPSK space optical communication system.The main research contents are as follows.(1)The experimental platform of 1.25GBaud QPSK spatial coherent optical communication system was built.Aiming at the relative delay of IQ two channels caused by non-strict equal length of cable and PCB in the platform,a receiver multi-channel data alignment algorithm based on pseudo-random binary sequence was designed and implemented.Based on stratix-V5SGXMA7K2F40C3,the proposed algorithm occupies 2%of the resources and the maximum clock constraint frequency can reach 179.37MHz.1.25GBuad QPSK spatial coherent optical communication online experiment shows that the designed module can achieve IQ alignment function.(2)Aiming at the problem of high complexity of multiplication and square root in the traditional Gram-Schmidt Orthogonalization Procedure(GSOP)algorithm,a simplified GSOP Orthogonalization algorithm is designed.Reduced multipliers by 33%and avoided square root calculations.The off-line experimental results show that the performance of the proposed algorithm is only about 1dB lower than that of the traditional algorithm.The online experiment results of 1.25GBuad QPSK spatial coherent optical communication show that the sensitivity of the proposed receiver can reach-32dBm@lE-3 in the case of weak turbulence,which is similar to its offline verification performance.(3)As the real-time capability of the Numerical Control Oscillator(NCO)in the traditional parallel clock synchronization algorithm cannot meet the requirements of high-speed data processing in 1.25GBaud system,a parallel clock synchronization algorithm based on shared NCO is proposed in this paper.Based on stratix-V-5SGXMA7K2F40C3 chip,the maximum clock constraint frequency of the proposed algorithm can reach 166.28MHz,which can meet the 156.25MHz timing requirements of 1.25GBaud system.The off-line experimental results show that the proposed algorithm saves 30%of the resources compared with the traditional algorithm,and the receiver sensitivity degrades only about 1dB.The online experiment results of 1.25GBuad QPSK spatial coherent optical communication show that the sensitivity of the proposed receiver can reach-32dBm@1E-3 in the case of weak turbulence,which is similar to its offline verification performance.