FPGA-based Fixed Floating Point Integrated FPU Design

FPU(Float-point Processing Unit)is a floating point computing unit inside the chip,which undertakes all the floating point computing tasks inside the chip,and the performance of the FPU determines the floating point computing power of the entire chip.Although the current FPU computing power is constantly improving with the iteration of the chip,after investigation,it is found that almost all FPUs have the following problems.The first is that the current FPU only has floating-point computing capabilities,but not fixed-point computing capabilities,and fixed-point computing tasks are assigned to arithmetic logic units(ALUs).Second,current FPUs will implement all floating-point functions with combinatorial logic.Third,the switching overhead between fixed-point computing and floating-point computing is too large,requiring multiple cycles to complete,which will lead to a serious decrease in computing efficiency in the case of frequent switching scenarios.Finally,many FPUs have fixed and immutable precision,or only support single-and double-precision calculations.Therefore,in order to solve the above four problems,this paper designs a fixed floating point integrated hardware computing unit based on the FPGA platform,that is,a fixed floating point integrated FPU.This paper specifically does the following work:In view of the resource utilization problem,this paper proposes to extract the fixed-point computing module ADD and MUL by analyzing the floating-point calculation characteristics and using the module splitting method,and use them as common computing submodules,and both fixed floating points can be called;In view of the problem of operating frequency,on the basis of extracting the computing submodule,this paper splits the pre-processing part and the post-processing part at the same time,extracts the common processing sub-modules HD,ALIGN,NORM,etc.,and connects the sub-modules to form a pipeline,which reduces the length of the combined path and improves the operating frequency.Aiming at the fixed floating-point mode switching problem,this paper adds the fixed float conversion control words I2F and F2I to achieve the purpose of quickly switching the fixed float calculation mode.In view of the accuracy problem,this paper innovatively adds a three-bit bit_div control word,selects the current calculation accuracy through the control word,and supports the minimum 8 bits to the highest 64 bits of fixed floating point calculation.To verify the correctness of the design,this article verifies the FPU through two methods:functional simulation and on-board verification.During the on-board test,the FPU successfully ran at 200MHz.The verification results show that this FPU has the ability to quickly switch between variable precision and fixed floating-point functions.It can calculate the fixed-point accuracy including IN8/INT16/INT32/INT64,the floating point accuracy includes FP8(E5M2,E4M3)/FP16/BF16/FP32/FP64,and the overhead of fixed floating point calculation switching is only 1 cycle,the accuracy is variable so that it can adapt to most computing scenarios,and the fast switching of fixed floating point mode can greatly improve the computing efficiency.In addition,the FPU has the ability to complete a variety of typical types of floating-point and fixed-point calculations,including fixed-point addition,subtraction,multiplication and division,surplus,MAC,SIN,COS,and floating-point addition,subtraction,multiplication and division,and floating-point MAC,with rich computing functions to meet the common fixed floating point requirements.In terms of resource occupancy and performance,the LUT occupancy rate is 16%,the LUTRAM occupancy rate is 7%,the FF occupancy rate is 15%,the BRAM occupancy rate is 26%,the IO occupancy rate is 43%,and the MMCM occupancy rate is 10%.The power estimated by VIVADO is about 800mW,and the 8bit floating point computing power reaches 1.6GFlops.