Design Of Fractional-N Phase-Locked Loop And Clock Generator For Qubit Measurement And Control

Quantum computing systems based on superconducting quantum chips or semiconductor quantum chips typically include quantum chips operating in the mK temperature region and classical measurement and control systems operating at room temperature.The large volume and cumbersome wiring of classical measurement and control systems seriously restrict the integrated development of quantum computers.To solve this problem,it is necessary to miniaturize and integrate the measurement and control system.Therefore,this thesis focuses on the miniaturization of the measurement and control system,and conducts relevant research and design based on the clock signal requirements of the measurement and control system.This thesis first briefly introduces quantum computing,expounds the necessity of miniaturization of quantum bit measurement and control systems,analyzes the constituent modules and measurement and control principles of the measurement and control system,and investigates the development status of phase locked loops and quantum bit measurement and control systems at home and abroad.Subsequently,this thesis analyzes the basic principle of the charge pump phase locked loop,explains in detail the various performance parameters of the charge pump phase locked loop,analyzes and establishes the loop model and noise model of the charge pump phase locked loop,laying a solid theoretical foundation for the subsequent specific circuit design and implementation.Secondly,based on the requirements of quantum bit measurement and control systems for radio frequency signals,this thesis uses the SMIC 40 nm process and a digital analog hybrid design method to complete a fractional frequency division charge pump phase locked loop with an output range of 6.02 GHz to 6.75 GHz.When the output frequency is 6.464 GHz,the phase noise is-97.86 dBc/Hz@1 kHz,-118.32 dBc/Hz＠1 MHz,The RMS jitter between 100 Hz～100 MHz is 213 fs,the spurious is less than-61.92 dBc,the power consumption is 9 mW,and the comprehensive performance factor FOM is-243.9 dB.The overall post simulation results show that the designed phase locked loop meets the specification requirements and can provide stable RF clock signals for quantum bit measurement and control.Finally,this thesis implements a clock generator based on a charge pump phase locked loop using the Nexchip 110nm process,and submits a chip.When the output frequency is 400 MHz,the phase noise is-96.08 dBc/Hz@1kHz,-112.82 dBc/Hz@1 MHz,the RMS jitter between 1 kHz～100 MHz is 1.81 ps,spurious less than-62.36 dBc,power consumption 13.5mW,The comprehensive performance factor FOM is-224.8 dB.The overall post simulation results show that the designed phase locked loop meets the specification requirements and can provide stable intermediate frequency clock signals for quantum bit measurement and control.The following innovations exist in this thesis:(1)This thesis focuses on the impact of tuning gain changes on the loop characteristics of traditional broadband LC voltage controlled oscillators.A combination of series and parallel switched capacitor arrays is used to reduce the tuning gain changes and the fluctuation of loop bandwidth;(2)This thesis focuses on the poor phase noise of traditional ring oscillators and adds a new edge receiving path to the traditional differential delay unit,reducing the phase noise of the ring oscillator.