Design Of Low Noise Clock Multiphase Generator

With the development of integrated circuits,wireless communication devices,intelligent sensing devices continue to enter people’s lives,while with the complexity of application scenarios and diversification of demand,making the requirements of integrated circuit chips more and more stringent,people are pursuing higher precision and higher quality integrated circuit chips.Phase locked loop is a clock generator,widely used in a variety of high-speed,high-precision circuits,is an indispensable part of the circuit.For the time digital converter（TDC）,the clock determines the accuracy and resolution of the entire system,in order to get a high precision TDC,the performance of the clock signal is very critical.So in order to meet the needs of a high precision TDC,research on high performance clock generators is carried out,that is,a low noise,low jitter clock generator is needed.The main research contents of this paper are:1.Based on the SMIC 55nm process,a low-noise,low-jitter subsampling phase-locked loop circuit is designed according to the design requirements.The analysis and design of each circuit module and simulation verification of the overall circuit have been carried out,and the simulation verification of the loop has been carried out,and the corresponding parameter indexes have been extracted.2.The subsampling phase-locked loop individual modules and the overall layout were analyzed and designed,and the overall layout of the subsampling phase-locked loop SSPL was completed.The design was obtained in SMIC 55nm process with a supply voltage of 1.2V,input reference clock of 50MHz and output clock range of 2.15GHz-2.62GHz with sub-sampling phase-locked loop,of which the locking time of the loop is 3.72us when the output is 2.4GHz,power consumption is 6.266m W,area is about 0.2275mm~2,reference spurious spur is-47.9d Bc,output phase noise is-120.04d Bc/Hz@100KHz,-122.49d Bc/Hz@1MHz,-143.98d Bc/Hz@10MHz,root mean square jitter RMS-jitter is 146.1fs,and the quality factor of the phase-locked loop FOMjitter=-248.7dB,which meets the design requirements.