Font Size: a A A

Research And Implementation Of Digital Channelized Receiver Signal Detection Technology

Posted on:2024-01-27Degree:MasterType:Thesis
Country:ChinaCandidate:L YangFull Text:PDF
GTID:2568306941997209Subject:Communication Engineering (including broadband network, mobile communication, etc.) (Professional Degree)
Abstract/Summary:PDF Full Text Request
With the increasing complexity of the electromagnetic environment of radar electronic warfare and the complex and changeable battlefield information,digital channelized receivers with the advantages of large dynamic range,strong real-time,high sensitivity,and fullprobability reception are widely used in modern warfare.In digital channelized receivers,the effective acquisition of signals,the effective filtering of signals by efficient channelized structures,the detection of sub-channel signals after channelization,and the effective extraction of Pulse Descriptor Word(PDW)data are all key problems to be solved in channelized receivers,which play a decisive role in subsequent signal sorting and recognition processing.This paper mainly focuses on the digital channelized receiver based on multiphase filtering and its subsequent sub-channel signal detection technology.The research completed in this paper is as follows:1.In terms of basic theory,starting from the basic principle of digital channelized receiver,the efficient structure of digital channelization based on multiphase filtering is studied,and its mathematical model is derived based on sampling theorem,signal multi-rate processing theory,channel division and arrangement,and relevant theoretical simulation results are given,which verifies the validity and correctness of the digital channelization structure based on multiphase filtering.2.In terms of sub-channel signal detection,aiming at the detection problem of sub-channel signal after channelization,a dynamic adaptive double-threshold signal detection algorithm based on the principle of unit average constant false alarm detection(CA-CFAR)and autocorrelation accumulation is proposed.The CA-CFAR principle is used to estimate the signal noise power,and in the case of high signal-to-noise ratio signal input,a dynamic adaptive high threshold is designed,which can directly determine the threshold of the channelized subsignal without other steps.In the case of low signal-to-noise ratio signal input,the output subchannel signal needs to be autocorrelation accumulation,and the dynamic adaptive low threshold is designed as the detection threshold to detect the sub-channel signal,the algorithm effectively solves the problem of real-time signal detection under high signal-to-noise ratio and the problem of weak signal detection under low signal-to-noise ratio,and the implementation is simple and has superior performance.In order to correctly extract the pulse descriptor(PDW)data,a method is given for the measurement of time domain parameters such as Pulse Width(PW),Time of Arrival(TOA),and Carrier Frequency(CF).Finally,a channel judgment method is proposed,which can judge narrowband signals and wideband signals located in the transition band,remove false channel numbers,and effectively solve the cross-channel signal judgment problem caused by uniform channelization.3.In terms of FPGA implementation,a digital channelized receiver based on multiphase filtering is realized based on the Field Programmable Gate Array(FPGA)platform,and the overall design scheme of FPGA and the key structural design methods in each module are given.In order to realize the correct acquisition and synchronization of AD9680 multi-channel signals,a data acquisition module is designed based on JESD204 B interface,and the acquisition of eight IF signals is successfully completed.Based on the multiphase filter channelization module,the complete signal detection process is realized,and the time domain parameters such as pulse width(PW),arrival time(TOA),and carrier frequency(CF)are smoothly extracted.In order to realize the data transmission and command interaction between FPGA and digital signal processor(DSP),the two-way communication between the two is completed based on the SRIO interface,and then the functional verification of each module is carried out to verify the feasibility and effectiveness of the overall design scheme of digital channelized receiver based on multiphase filtering.
Keywords/Search Tags:Digital channelization, Signal detection, FPGA, JESD204B protocol
PDF Full Text Request
Related items