Research On Key Technology Of DSC Video Compression And Hardware Design

In recent years,ultra high definition 4K resolution display has gradually become the mainstream of the market,8K or even 10 K will enter our life.The continuous improvement of video resolution will inevitably consume more display link bandwidth,and the existed display interface can not meet the rapid growth of bandwidth requirements.Although there were many video compression standards in the market,these standards were not conducive to hardware implementation because of their complex logic.Display stream compression(DSC)standard is a lightweight video compression algorithm.At the same time,DSC standard can use less hardware resources to achieve real-time video compression and visual lossless effect.Therefore,with the study of DSC algorithm,the hardware circuit of the key modules in DSC encoder was designed,and their functions were simulated on FPGA platform.In addition,inspired by the coding scheme of DSC,an on-chip video compression algorithm was proposed to compress the video data before the output,in view of the problem that the direct output of the uncompressed video data from the image sensor would occupy a large transmission bandwidth.In this paper,firstly,the coding principle of DSC video compression algorithm is studied,and the data processing principle and process of color space conversion,prediction and quantization,color history index,rate control module in the encoder was analyzed,which lays a theoretical foundation for the design of the encoder.On this basis,the pipeline design idea is used to complete the hardware circuit design of each data processing module,which meets the requirements of real-time video compression.Next,the simulation model of each module in the encoder is built based on the working principle of the encoder,and the consistency between the output data and the algorithm design is analyzed.In this paper,each module of DSC encoder is designed based on the KC705 development board of Xilinx company,and the basic requirements of DSC encoder are realized.The simulation results show that the design can support RGB and YUV data input format,and support 8 bit/component 4:4:4 format video input.Through the design of pipeline,the encoder can meet the real-time processing rate of 1pixel/clock.This design can support the video compression ratio of 3:1.An image sensor on-chip video compression algorithm using the frame difference is proposed by combining the entropy coding scheme of DSC algorithm and the working principle of the image sensor.In this paper,a sensor-level video compression model is built based on the working principle of image sensor,and the proposed on-chip video compression algorithm is simulated.The simulation results show that when the block size is set to 4×4 and the threshold is set to 63,the compression algorithm using interframe difference coding can achieve the optimal compression effect.The algorithm achieves a compression effect of 1.72 bits/pixel in the absence of light and static condition.To sum up,the hardware circuit of the encoder and the on-chip video compression algorithm proposed in this paper can achieve better video compression.