Codec VLSI Design Of Display Stream Compression

With the developing of ultra-high-definition display technology,people are increasingly unable to meet low resolution,like 720 p,compared with high defination display.However,the technology corresponding to high-definition display is not perfect,a large amount of bitstream data flow requires better compression method,high-speed transmission path,high-performance display interface and a huge cache space,which lead to the sharp increase in equipment costs.In response to this problem,the Video Electronics Standards Association(VESA)proposes a Display Stream Compression standard(DSC),which can decrease the amount of high-resolution display bitstream to relieve the interface pressure.Therefore,it is necessary to use DSC display compression hardware system between display interface in future.In this paper,we study the DSC algorithm and realize the design of hardware.In order to improve the hardware performance,we proposed two-level parallel flow structure,which reduce the area overhead and improve the speed of operation.We design codec multiplexing structure to reduce the chip area.We also adaptive algorithm to ensure image quality.Based on the "virtual memory",we design the transmission configurable structure and use the self-test signal to reduce errors.Our structure supports 1080 p and 4K resolution images of 2: 1,3: 1 and 4: 1 compression display.Also,it can support 14 kinds of HDMI display protocol.We also increase transmission anti-jamming design to ensure the transmission independence between frames.We analyze and optimize the DSC algorithm.The two-level parallel codec structure is modeled and simulated in Verilog HDL.Two codec multiplexed structures are configured in code and decode separately to build the verification platform.Using the "golden model comparison method",the platform process verificated in different resolution.Finally,the logic of the design is analized in timing,area and power consumption.The implementations are able to process 60 frames per second for 1080 p sequences for FPGA and 60 frames per second for 4K sequences for ASIC.