Research On Non-volatile Sram With Double Rram Complementary Backup And Recovery

After the Static Random Access Memory(SRAM)is powered on again,the data cannot be recovered by itself until it is powered off.In order to make the SRAM nonvolatile,researchers designed Nonvolatile Static Random Access Memory(NVSRAM)with both nonvolatile and high-speed read-write capabilities.With the progress of technology,the decline ratio between the threshold voltage and the working voltage of the device is inconsistent,resulting in the increase of leakage power consumption of SRAM,while NVSRAM can reduce the leakage power consumption to zero by power off.Thus,the design of NVSRAM with highspeed backup and recovery capability is of far-reaching significance for the need to power on to recover the data in SRAM and reduce leakage power consumption of SRAM.Based on the non-volatile characteristics of Resistive Random Access Memory(RRAM),a new Nonvolatile Memory(NVM)cell is devised.Two RRAM devices are connected in series in the same direction,which improves the precision of NVM cell in restoring the potential of latch node.Using single transistor or complementary transistors to connect the common node of NVM cell with the latch node of standard SRAM cell,four NVSRAM cell structures,7T2 R,8T2R,8T4 R and 10T4 R,are devised.The full parallel backup and recovery circuit of the corresponding array is designed to solve the problem that when a single RRAM device recovers a single latch node,it needs additional write operation operations to initialize the NVSRAM cell latch node,which increases the recovery power consumption and delay overhead.The Layout of the devised four cells is designed under TSMC 65 nm process library,and it is verified by post-simulation.Functional simulation results show that the devised four cells achieve stable read-write,backup and recovery functions.The static simulation results show that the four devised cells show the read-write performance close to that of standard SRAM cells.At least96.23% of the standard SRAM cell Hold Static Noise Margin is retained for backup operations of the four cells under the FF process angle.Under the working voltage of 1V,the leakage power consumption of standard SRAM and backup and recovery power consumption of NVSRAM cells are simulated and analyzed.Cell holds data for 1ms,the devised 7T2 R,8T2R,8T4 R and 10T4 R cells have 26.43 X,23.86 X,8.43 X and 7.5X lower leakage power than standard SRAM cells,respectively.The longer the data retention time,the better the performance of NVSRAM cell in reducing leakage power consumption.According to the delay analysis,the minimum delays of cell backup and recovery data are 0.535 ns and 4.147 ns respectively,and the backup and recovery delay is not directly related to the array capacity.Simulation analysis shows that the delay of backup data ’0’ of the devised four cells using transmission gate synchronous voltage is basically the same as that of single transistor structure,and the delay of backup data ’1’ is reduced by 1.83X;The recovery delay of differential structure is 1.81 X lower than that of single-end structure.