Research On Row-column Bidirectional In-memory Computing Subtraction Calculation Circuit Based On 8T SRAM

In the past decade,the rapid development of artificial intelligence(AI)technology has made important progress in the fields of speech recognition,pattern recognition and intelligent medical care.However,the rapid development of science and technology has brought data processing dilemmas to computers,and the algorithms used in common AI chips need to train a large amount of data to obtain accurate data,which has led to more time and power consumption required by the device in processing data.Ai-specific chips have since been proposed by researchers,whose main purpose is to alleviate the time and power consumption of central processing unit(CPU)on data processing,and its research and development has made some progress in recent years.But whether it is the CPU processing data or the use of AI professional chips,these are irresistible to encounter the "memory wall" problem.The main reason is that the research direction of the computing module is speed,while the memory module pursues large capacity,which leads to an imbalance in the access speed of the two.As a result,the large amount of data processing in between brings more waiting times and power consumption to carry data.In order to solve these difficult problems,the computing in memory(CIM)architecture was proposed.The memory computing architecture is to integrate storage and computing,in essence,breaking the boundaries,the memory of the memory computing architecture can not only access the data,but also carry out different types of operations,which saves the time of handling data and power consumption,and will greatly improve the performance of the chip.static random access memory(SRAM)can be fully compatible with CMOS process and has the advantage of fast access,acting as a cache in a high-performance processor,and its multitube structure makes the implementation of multiple operations more feasible,so researchers have carried out a large number of in-memory computing studies on SRAM.This paper proposes a four-word line four-line 8T SRAM unit and designs a bidirectional subtraction model of adjusting word line NMOS transmission tube width ratio W/L based on8 T unit.Four units are a Block,and the adjusted word line NMOS transmission tube width ratio W/L is 1:2:4:8.The reduction P is stored from top to bottom in the unit,the reduction D is input through the word line control signal,and the weight-weighted subtraction calculation architecture is realized through the W/L width ratio of the transmission tube NMOS of the storage unit in the original cell array.The system carried out a lot of simulation verification under the 28 nm CMOS process,the storage unit array is 64×64,and finally verified that the subtraction model has good linear stability,the minimum ΔV is about 3mV,throughput of 48 GOPS and power consumption of 1.25 TOPS / W,small power consumption.