Design Of Multiplication Computing In-memory Based On Traditional SRAM

With the development of machine learning,image recognition,networking,and other emerging fields,the traditional computing architecture cannot meet the requirements of processor speed and energy efficiency in processing of computing tasks based on big data.Inmemory computing is different from the traditional computing architecture.It combines the storage module and the computing module of the system so that the data processing steps of the system can be directly completed in the memory,realizing the integration and computing.Inmemory computing saves the data transmission of the storage module to the computing module,not only saves energy consumption but also further improves the data processing speed.Static random access memory(SRAM)has been the focus on scholars’ research on in memory computing because of its high speed and low power consumption.This article proposes an inmemory multiplication based on traditional 6T SRAM.The main work of this paper are as follows:This article first introduces the traditional von Neumann computing architecture and its bottlenecks and analyzes several existing methods to solve the von Neumann bottleneck.The advantages and significance of the in-memory computing architecture is highlighted by comparison.It describes the structure,working principle of SRAM circuit and several computing circuits based on SRAM memory.Based on the above analysis,this paper proposes an in-memory multiplication computing method based on traditional 6T SRAM.The circuit has two working modes: traditional SRAM working mode and in-memory multiplication computing mode.When the circuit works in the memory multiplication computing mode,the circuit can store the two multipliers in the memory array of binary form as needed,and change the bit line to the memory cell by mounting different capacitors on the bit line of the memory array.The discharge speed of the bit line makes each memory cell discharge to different degrees after the word line of the current row is turned on.After the discharge is completed,the total discharge of the bit line are the result of the multiplication operation.At last,functional simulation and power consumption calculation of the designed circuit are carried out.In terms of power consumption,compared with the traditional computing mode,proposed circuit saves about 60 times of energy consumption of the same array size,it shows that the circuit has the advantages of high stability and low power consumption.