Research And Design On Key Circuits Of RF Transceiver Chip Based On 65nm Silicon CMOS Technology

With the gradual improvement of the process of economic globalization and social informatization,people’s increasing demand for life constantly poses new challenges to the performance of wireless communication system.As the core component of wireless communication system,RF transceiver chip directly affects the core performance of wireless communication system,and its research and design has set off a new upsurge in academia and industry.At the same time,with the rapid development of semiconductor industry and integrated circuit industry,the characteristic frequency and minimum size of silicon CMOS（Complementary Metal Oxide Semiconductor）process are constantly optimized,which provides the foundation for realizing low cost and high performance RF transceiver chip.Low Noise Amplifier（LNA）and Power Amplifier（PA）are the first and last active modules in the RF transceiver channel,respectively.Their performance will directly determine the information and data quality of wireless communication.Therefore,LNA and PA with excellent performance and low cost have become the current research hotspot.Based on the low-cost and highly integrated TSMC 65nm silicon based CMOS process,this paper carried out research and design for LNA and PA.The specific work and innovations of this paper are as follows:1.This paper designs and implements a high-gain miniaturized LNA for x-band application.The LNA adopts a two-stage differential common source topology.By introducing the neutralization capacitor technology,the design effectively inhibits the Miller effect caused by the parasitic capacitance between the transistor gate and drain,thus improving the gain and stability of the circuit.At the same time,the input,interstage and output matching networks of LNA are all composed of on-chip transformers and barons with shunt capacitors,which can not only optimize the circuit area but also reduce the demand of impedance matching network for transformers with high coupling coefficient and increase the design freedom.The measured results show that the maximum gain of the proposed LNA is 22.9d B,the minimum Noise Figure（NF）is 2.8d B,and the DC power consumption is 49m W in the bandwidth of 9.6～12.7GHz.The core area of the chip is only330μm×730μm.2.In order to further improve the bandwidth of RF receiving channel,this paper designs a broadband miniaturized low noise amplifier working in X-band.The overall architecture of the circuit is composed of a common source stage and a common source common gate stage（cascode）.For the input terminal of LNA,a transformer feedback structure is proposed in this paper,which makes the input impedance independent of frequency in the ideal state to achieve wideband matching.At the same time,inductive peaking technology is introduced in the inter-stage and common gate stage of cascode respectively,which effectively reduces the noise figure and improves the bandwidth performance.The simulation results show that the LNA achieves 14.6±2d B gain and2.5～3.3d B noise figure in the bandwidth range of 8.5～12.5GHz.The LNA has a DC power consumption of 20.8m W and a core size of 410μm×870μm.3.Aiming at the application requirements of RF transmission channel for high radiation distance,this paper designs and implements a Ka band two-channel synthetic PA for high output power.The PA is composed of a drive stage and a power stage.The main part of the amplifier adopts differential cascode structure with neutralizing capacitance to improve the PA’s output swing,output power,stability and gain of the PA.At the same time,this design adopts the Transformer series power synthesis network for two way high power synthesis.A power synthesis network with an LC resonant network at the end is proposed.This structure can achieve the optimal load impedance matching of PA,reduce the number of simulation iterations of the power synthesis network,improve the design efficiency,and achieve a good matching with the 50Ωload.The simulation results show that the maximum gain of PA at 40GHz is 26.6d B,its 3d B bandwidth is 37-43GHz,saturation output power(P_sat)is 21.4d Bm,maximum power added efficiency(PAE_max)is 13.3%,and the output power of 1d B compression point(OP_{1d B})is 21.1d Bm.The core size is 685μm×380μm.The figure of Merit（FOM）of PA is 91.3.