Design Of Computing-in-Memory Circuit For Transposed Multi-Bit Multiplication Based On 8T SRAM

Recently,with the fast-growing artificial intelligence（AI）and 5G communication technology,the demand for data volume and computing volume is expanding,and the requirements for low power consumption are becoming more and more severe.Almost all the leading computer systems are developed based on the von Neumann architecture in the word.A typical feature of the von Neumann architecture is the physical separation of the memory unit and the arithmetic logic unit（ALU）,which leads to the issue of“memory wall”.One possible method to overcome the von Neumann bottleneck and meet the growing demand for better computing performance is Computing-In-Memory（CIM）.CIM technology not only does not require frequent data transmission between the storage unit and the ALU but can also realize the parallel calculation of multi-horizontal or multi-vertical data.Therefore,CIM can alleviate the problem of“memory wall”bottlenecks,increase computing speed and reduce energy consumption.This paper proposes a transposable multi-bit multiplication computing-in-memory circuit based on 8-transistor（8T）Static Random Access Memory（SRAM）.1)The transposable weight circuit based on 8T cell can realize vertical or horizontal in-memory calculation;2)Multiplier based on Cascode Current Mirror（CCM）to ensure linearity in the calculation process.The 8T storage cell adopts the read–write isolation path,which can increase the read noise margin and alleviate the read-disturb issue.The proposed circuits have two operation modes,including basic SRAM operations and CIM operations.For SRAM mode,the data can be read-write through 6T in proposed 8T cell.For CIM mode,the column-wise multibit multiplication can be realized by activating multi-row data and clamping the voltage of read bit line.Similarly,the row-wise multibit multiplication can be achieved by activating multi-column data and clamping the voltage of source line.To achieve low-overhead and more efficient quantification,a current-type low-overhead counter quantization circuit is proposed,which consists of counters,cascaded asymmetric inverters,and other combinational logic circuits.This quantification circuit can quantify the multiplication results by sensing the flip voltage(1(1of the asymmetric inverter.In this paper,the simulation verification of 64×64（4Kb）storage array with 256 TWB for bidirectional multibit multiplication operations is completed in 28 nm CMOS technology.The quantization count time of the multiplication output result is inversely proportional to the output current.Thus,the smaller the calculating results,the higher the quantization accuracy.An 8-b output precision can be obtained using a low-overhead counter-type quantization circuit.At the supply voltage of 0.9V,the energy consumption of column and row multiplication operation are 57.65f J/bit and 58.94f J/bit,respectively.The multi-bit multiplication energy efficiency is16.97-84.1TOPS/W;this energy efficiency improvement is up to 1.5–3 times higher than the existing CIM works.