Research And Design Of DRAM Data Error Correction Circuit

In recent years,with the improvement of science and technology,the rapid development of integrated circuits,memory chips and other fields,especially the chip industry has become the most popular topic in the past two years.Memory chips need to read data quickly and accurately.However,when the memory is read and write,it is inevitable to produce wrong data,which often affects the normal operation of the memory.In order to solve these problems and make the memory store data more efficiently,DRAM data correction needs to be done,the memory needs check and scrub every once in a while,so the Error Check and Scrub(ECS)mode is required.Introduce the research status of Memory chips,and analyze the basic architecture and working principle of Dynamic Random Access Memory(DRAM),as well as the basic command and timing control.DRAM has the advantages of high integrated,low power consumption and low price,and is widely used in memory chips.Error check and Scrub(ECS)mode is one of the most important modules in DDR5,in which ECS mode operation control and internal self-generated command are key technologies.Research two kinds of ECS operation modes including manual ECS operation mode and automatic ECS operation mode,as well as the design of manual ECS control circuit and automatic ECS control circuit.By default,ECS operations are performed automatically when DRAM is running,but in manual ECS control circuits manual ECS mode operations need to be enabled through mode register configuration and then through the address decoder.Manual ECS operations are simple but can only be implemented if an external controller sends a multifunction command(MPC).Therefore,error checking and cleaning cannot be performed during shutdown.In order to solve this problem,an automatic ECS control circuit is designed in this paper.When the mode register is closed,the ECS operation command can be generated by means of self-refresh.Under orders from refresh every once in a while to steal a refresh ECS operation command is used to do,so we introduce the counter number to calculate since the refresh command,the meter to a certain number of after some logic to generate the ECS operation command automatically,so as to realize the mode register under closed also can implement error and checking.After the ECS operation command is generated,the DRAM starts to perform internal READ,modify,and WRITE cycles.Therefore,complete READ and WRITE operations are required.At the same time,ACTIVE,READ,WRITE,and PRECHARGE internal self-generated commands are implemented.In this paper,we design three methods to realize the internal self-generating command,with the help of shift register,delay chain and ring oscillator,through the waveform view of the specific function,and compared the advantages and disadvantages of the three methods,choose a more appropriate circuit.