Optimization And Research Of Clock Tree For Vehicle-mounted Video Transmission Chip Based On 40nm Proces

In recent years,with the rapid development of the semiconductor industry and the new energy industry and the emergence of smart cars,the demand for automotive chips in the automotive market has increased day by day.Considering the sensitivity of driving safety,an in-vehicle chip needs to transmit and process data stably and efficiently in a complex environment,which greatly increases the design complexity and implementation difficulty of the in-vehicle chip.Under the background of "car chip shortage",studying the physical design of digital-analog hybrid car chips under mature technology has important practical significance for accelerating chip timing closure and improving chip yield and reliability.It is useful for digital-analog hybrid chip design and module level.The clock tree design of the digital chip is of great reference.In this paper,based on SMIC 40 nm process,a digital module with a digital-analog hybrid vehicle video transmission chip is designed and implemented.The highest frequency of this module is 320 MHz,the size is 3043um*2658um,the scale is 6.28 million gates,with 1049 I/O ports and 22 hard macros.This thesis is based on the physical realization process of the digital module of the digital-analog hybrid vehicle video transmission chip before wiring.It studies the difficulty of the timing of the module-level digital chip design.It focuses on the analysis of the clock network structure with added test logic,and proposes the following clock tree synthesis and optimized strategy:(1)By analyzing the clock structure between the input logic and the digital module,the segmented clock tree synthesis strategy is used to set a breakpoint at the clock selection unit to segment the function clock.The results show that compared with the traditional clock tree synthesis,the average insertion delay of the critical clock path is reduced by 45.99%,the number of violation paths checked by the input interface setup time is reduced by 48.66%,the total negative slack(TNS)is reduced by 78.68%,and the number of violation paths checked by hold time is reduced by 79.09%.The total negative slack was reduced by 57.68%.(2)By analyzing the logical asynchronous relationship between the functional logic and the test logic,the clock selection unit is preprocessed before layout,and the pin of the test logic input clock selection unit is set as the leaf node of the test clock,so that the clock tree structure is optimized.The results show that compared with the traditional clock tree synthesis,the number of violation paths for the internal timing setup time check of digital logic is reduced by 93.39%,and the total negative slack is reduced by99.14%,the number of violation paths of the holding time check is reduced by 26.69%,and the total negative slack is reduced by 14.30%,and the proportion of standard cell density is reduced by 10.06%.(3)Aiming at the interface timing problem caused by the physical distance between the multiplexing modules on the top of the chip,a multi-source clock tree synthesis strategy based on the configuration of the anchor driver to guide the direction of the clock tree is proposed.The results show that,compared with the traditional clock tree synthesis,the number of illegal paths in the output interface setup time check is reduced by 84.65%,and the total negative slack is reduced by 98.07%;the number of illegal paths in the hold time check is reduced by 87.29%,and the total negative slack is reduced by 79.96%.