FPGA Hardware Implementation Of Real-time Video Image Scaling System

Digital video image has the characteristics of large amount of data and high real-time performance.The processing of video image is the key problem in the field of image processing.The software algorithm of PC side is used to process images,which requires a long running time,cannot meet the requirements of real-time display,and the equipment required takes up a large space,resulting in large limitations of software processing.It is usually used in the fields with high requirements for image quality but no real-time requirements,such as medical treatment.The Field Programmable Gate Array(FPGA)is used to implement hardware circuit for image processing algorithm,which meets the real-time requirement in terms of speed and achieves a good level in the final image quality with different image processing algorithms.The research content of this paper is the zooming processing of real-time video image.The resolution of the source video collected by the camera is fixed,but when the source video is displayed on different displays,there will be inconsistency between the resolution of the source video and the resolution of the display.To solve this problem,the real-time video image zooming system is built using FPGA as the hardware platform.To meet the needs of different resolution display.This paper studies three commonly used image scaling algorithms,analyzes their theoretical basis,and simulates these three algorithms using MATLAB software.The complexity of the simulation results and the realization of the algorithm hardware affects privacy,and selects the nearest neighbor algorithm and bilinear interpolation algorithm as the image scaling algorithm.The host computer sends serial port command to control the output of video image with target resolution.This paper adopts the modular design idea,which is divided into: image acquisition module,cross-clock FIFO module,image scaling module,image cache module,HDMI display module,serial port parsing module.In the image scaling module,a RFIFO cache scheme is proposed for the cache of pixel values of the source image,and the RFIFO read and write control strategy is given,as well as the generation of coordinates and coefficients and the final interpolation operation.Verilog language and dedicated IP core were used to complete the design of each module,and the preliminary functional simulation verification of each module was carried out.After the design of the whole system was completed,the bitstream file was generated after integration and implementation,and the file was burned into the chip,and the key signals were captured by ILA logic analyzer to complete the final board level verification.The verification results show that the image scaling system designed in this paper is available,can output more than 24 frames of video images,the output picture is clear without distortion,to meet People’s Daily needs.