Bulk Silicon GaN Half-Bridge Driver Chip Low-Latency Level-Shift Circuit Design

Compared with silicon-based power devices,GaN power devices have the advantages of fast switching speed and high electron saturation rate,which are very suitable for systems with high operating frequency and high power density.In such systems,GaN power devices often require halfbridge driver chip control.One of the core technologies of the half-bridge driver chip is the level shift technology,whose performance directly affects the transmission delay and reliability of the chip.In the bulk silicon process,the traditional level shift technology is difficult to apply to the driver chip of GaN devices,so it is of great research significance to design a level shift circuit that meets the requirements of the GaN half-bridge driver chip.Firstly,this thesis expounds the working principle of the level shift circuit,and analyzes the delay characteristics and reliability of the level shift circuit in detail.The traditional level shift circuit needs to increase the filter width to filter out d V/dt noise,and the increase of the filter width leads to an increase in delay,which cannot take into account the requirements of low delay and high reliability.Based on the traditional level shift circuit,this thesis designs a low delay level shift circuit with a noise detection circuit and a current compensator.After detecting the d V/dt noise,the noise detection circuit generates a displacement current,which forms a voltage drop through the resistor and triggers the current compensator.Then,the current compensator that is turned on provides a current bleeder path to cancel the signal interference caused by d V/dt noise,and finally achieves the best compromise between high reliability and low delay.This thesis is based on the bulk silicon 0.8μm 600 V high voltage BCD process for simulation,layout drawing and tapeout.According to the test results: Under the condition that the power supply voltage is 15 V and the operating frequency is 1MHz,the high-side turn-on delay and turn-off delay are 28.7ns and 28.5ns respectively,the quiescent current is 285.1μA,and the d V/dt resistance is greater than 100 V /ns,reaching the design target.