Research On Performance Of NCFET Devices Which Is Based On Negative Capacitance Characteristics Of Ferroelectric Materials

Emerging technologies such as Internet of everything,artificial intelligence and machine learning have put forward higher demands on the performance,power consumption and volume of integrated circuits.Since its birth,integrated circuit has been developing rapidly in accordance with Moore’s law.The size reduction of the basic unit metal oxide semiconductor field effect transistor（MOSFET）makes the transistor density grow rapidly,making the MOSFET speed up,cost,power consumption and so on reduce.As the carrier in traditional MOSFET obeys Boltzmann statistical distribution,subthreshold swing（SS）is higher than 60 m V/dec at room temperature,which seriously limits the further improvement of MOSFET performance.Negative capacitance field effect transistor（NCFET）is one of the most promising candidates for low power consumption devices.Compared with MOSFET,NCFET solves the above problems effectively by adding ferroelectric films which have negative capacitance effect into the gate.Relying on National Engineering Laboratory for High Density Integrated Circuit Packaging Technology,our group successfully developed splendid ferroelectric film 0.85Bi Ti_0.1Fe_0.8Mg_0.1O₃-0.15Ca Ti O₃（BTFM-CTO）.Devices based on Ga As substrates are widely used for their high electron mobility and relatively wide bandgap which have potential to further increase the ratio of on current to off current.In this paper,based on the experimental data of BTFM-CTO,the negative capacitance model of BTFM-CTO based on Ga As is established in TCAD Sentaurus semiconductor simulation software.Aiming at the design of superior performance NCFET,fluctuation of gate control ability of NC-Fin FET and interface state of Fe FET memory,models of MOSFET,Fin FET and GAAFET are established and detailed simulations,researches and analysis are carried out on NCFET,NC-Fin FET,Fe-Fin FET and Fe-GAAFET.The main contributions and innovations of this academic dissertation include the following three parts:（1）Parameters related to NCFET structure can change its intrinsic capacitance,which will change the capacitance match of NCFET and significantly affect its performance.Based on TCAD Sentaurus semiconductor simulation software,we explore the effects of Ga As-NCFET structure parameters on capacitance match,gate voltage amplification effect,negative differential resistance effect,transfer and output characteristics.What is more,carrier mobility,energy band diagram,channel surface potential and substrate capacitance are also investigated to accurately analyze the simulation results.Simulation results indicate these factors have effects on capacitances match.Moreover,effects such as negative differential resistance（NDR）,gate voltage amplification（GVA）,short channel effect（SCE）,and saturation of carrier mobility（SCM）wax and wane.The competition between these effects makes the performance tend to not monotonous vary with factors and highly depend on other parameters or voltage bias.The structural parameters of NCFET are optimized based on simulation results and analysis.Simulation results show that Ga As-NCFET with BTFM-CTO film providing negative capacitance has a low SS value（44.9 m V/dec）.At a supply voltage of 0.6 V,ratio of the on current to off current is 1.2×10⁹.This demonstrates that BTFM-CTO is one of the ideal candidate ferroelectric materials for Ga As NCFET.（2）Driving strength of Fin FET is defined by width and height of channel.However,the size change of Fin FET will inevitably lead to the change of gate control and thus result in the fluctuation of other performance.NC effect endows the NC-Fin FET with steep SS,reinforced gate control,and superior performance.The variation of the structure parameters affects the capacitance match and the distribution of polarization and channel surface potential which further cause the change of the gate control capability.Considering that the effects of structure parameters on gate control may be related to the properties of ferroelectric film,PZT film which has relatively superior negative capacitance,BTFM-CTO and Hf O₂are used as dielectric films in simulation.Through detailed simulation of NC-Fin FET,the influence of structural parameters related to gate control on the transfer performance of NC-Fin FET was explored.In addition,the distribution of channel surface potential and ferroelectric polarization are studied,which provides reference for the analysis of simulation results.The simulation results show that the two effects mentioned above can to some extent balance out if given suitable enough capacitor match,which means that the fluctuation of gate control and threshold voltage can be significantly reduced.Therefore,the driving strength of NC-Fin FET is expected to be adjusted by changing the size and multi-channel Fin FET is not necessary.The extremely low power consumption and supply voltage NC-Fin FET designed by us has a SS value of 37 m V/sec with only 0.25 V supply voltage.Its I_ONand I_OFFare2.2×10^-6and 7.1×10^-13A,respectively。（3）The performance and reliability of Fe FET memory mainly depend on the control of ferroelectric polarization on threshold voltage,and the interfacial state is one of the main causes that threshold voltage fluctuates,which seriously reduce the reliability of data reading and storage.In this paper,based on Fe-Fin FET and Fe-GAAFET structure,the influence of interfacial states density and energy level position on Fe FET performance is explored through detailed simulation analysis,and the performance of Fe FET memory is quantified by two parameters:storage window（MW）and noise tolerance（RM）.The simulation results show that when the density of interfacial states increases or the energy level position is close to the conduction band or valence band,the leakage current increases when the gate voltage is negative,the drain current in the subthreshold region decreases,and SS increases.Increasing the gate voltage can reduce the influence of interfacial states fluctuation on the performance of Fe FET memory.Compared with Fe-Fin FET,although the SS of Fe-GAAFET is significantly separated when changing the gate voltage scanning direction and its sensitivity to interfacial states variation is weaker,the relatively small MW and RM of Fe-GAAFET seriously cut down the reliability and stability of Fe FET memory,posing limit on its application.This may be related to the match of capacitance.