Research And Design Of High-speed Split-sampling In Time-interleaved SAR ADC

Analog to Digital Converter(ADC)converts Analog signal to Digital signal,is an important bridge between Analog and Digital communication,widely used in all kinds of Digital communication system.As an important part of ADC front-end circuit,Track and hold(THA)greatly affects the performance of the overall ADC.Therefore,the study of high-speed and high-precision sampling-hold circuit is of great significance to the research of high-performance ADC.This thesis investigated the research status of TI ADC and high-speed sampling-holding circuit at home and abroad,analyzed the common front-end sampling architecture to determine the overall structure of the design,and analyzed the non-ideal effect,which is beneficial to the specific design of the circuit.A high-speed spilt-sampling hold circuit for TI ADC is designed,which includes sampling switch,input buffer,interstage buffer and multiphase clock generation circuit.The first level of sampling switch is grid voltage bootstrap type,which is used to improve the overall circuit accuracy.The second level of sampling switch,considering the overall layout area,chooses complementary CMOS switch.Based on the traditional source follower structure,the nonlinear factors are analyzed,and a high linearity and high bandwidth input buffer is designed.When the input signal frequency is 793.75 MHz,the spurious dynamic range of the output signal is 78.71 d B,and the-3d B bandwidth of the circuit is 2.81 GHz.Level in order to make up for the gain loss of the input buffer,the buffer between the full differential loop amplifier as a buffer between the magnitude,separately introducing auxiliary op-amp to stabilize the output commonmode level,add the source degeneration resistance improvement of nonlinear circuits,and design the positive and negative charge on the cross coupling type pump respectively auxiliary op-amp and main circuit of power supply,When the input frequency is 396.875 MHz,the spurious dynamic range of the output signal is 69.3d B.An 8-phase clock generation circuit is designed to control the second-stage sample-hold circuit.Based on the 40 nm CMOS process,the specific circuit and layout of the high-speed split-sampling hold structure of the time-interleaved ADC are designed.The simulation results show that: the sinusoidal signal with the input frequency of 99.21875 MHz,the stray free dynamic range of the output signals of eight channels are all about 60.6d B,and the effective bits are all about 9.75 bit.The input frequency of the signal is 793.75 MHz.After the output of the eight channels is integrated with Matlab,the stray free dynamic range of the obtained signal is 55.13 d B and the effective bit is 8.81 bit.The power consumption of the circuit is 105.2m W,which meets the design requirements.