Research And Design Of Silicon-based Millimeter-wave Low Noise Amplifier

The current RF spectrum has become increasingly crowded with only limited spectrum resources,which is difficult to meet the demand of modern high data rate communication.Mm-wave band has attracted the attention of academic and industrial researchers because of its wide bandwidth,small devices and easy integration.With the continuous reduction of process feature size,the cut-off frequency of silicon-based process（SiGe,CMOS,etc.）transistor constantly increases,which makes the realization of silicon-based millimeter wave circuit on chip becoming a reality.Compared with III-V group processes（Ga As,Ga N,In P,etc.）,silicon-based processes have the advantages of low cost,high reliability and good integration with baseband circuits.However,due to its low breakdown voltage,large parasitic capacitance and high substrate loss,there are still many challenges for circuit designers.Low noise amplifier（LNA）as the first active circuit of mm-wave receiver,plays a crucial role in the performance of the whole transceiver.In this paper,an in-depth study of silicon-based millimeter-wave low noise amplifiers is carried out.The main research work and innovations are as follows:1)Research on Ka-band LNA based on inductive coupled broadband matching technique.The LNA adopts a two-stage cascode structure as a whole,and proposes a broadband interstage matching circuit based on inductive coupling.This technique optimizes in-band gain flatness while expanding amplifier bandwidth by introducing weak coupling between two matching inductors.In addition,the DC bias,input matching,and noise performance of the LNA are analyzed and optimized in detail.This proposed LNA is fabricated in a 0.13μm SiGe BiCMOS process,and the chip covers a total area of 0.23mm².The chip measurement method utilizes the on-wafer test.The measurement results show that the LNA achieves a peak gain of 22d B,3-d B bandwidth of 25GHz（22～47GHz）with fractional bandwidth up to 72.5%,and the noise figure in the 3-d B frequency range is 3～4.3d B.The measured IP_{1d B} in the frequency range of 3-d B bandwidth is-23.9 to-22.6d Bm.The chip consumes a total power of 9.5m W with the supply voltage of 1.2V.2)Research on W-band low noise amplifier based on inductive coupled transconductance enhancement technique.The LNA consists of three stages with one single-ended cascode stage and two differential common source stages.The inductive coupling gm-boosting technique used in the LNA is deeply studied.By introducing coupling between the source inductance and gate inductance of the cascode transistor,this structure can simultaneously improve the gain and reduce the noise figure of the cascode.In addition,the transformer interstage matching technique and neutralization technique adopted by LNA are also analyzed and designed.Fabricated in a 65nm CMOS SOI process,the proposed W-band LNA covers a total area of 0.34mm² and the DC power consumption is 36m W.The chip measurement is carried out by on-wafer test method and the measured S-parameter shows that the LNA achieves a peak gain of 16.2d B,and the 3-d B bandwidth is 6GHz（92 to 98GHz）.Due to test equipment limitations,the LNA noise figure and 1-d B compression point are simulation results.The simulated noise figure in the frequency range of 89～97GHz are 7.2～7.7d B,and the simulation results of the IP_{1d B} are-10.1～-15.7 d Bm from 92 to 98GHz.In this dissertation,two LNAs for Ka-band and W-band millimeter-wave applications are designed based on SiGe BiCMOS process and CMOS SOI process,respectively.The simulation and measurement results show that the design theories and methods of the two LNAs have certain academic significance and engineering application value.