Design Techniques Of Silicon Monolithic Millimeter-Wave Amplifiers

With the progress and development of society,people’s demand for high commu-nication rate makes wireless communication technology develop rapidly.The radio fre-quency band below 10 GHz has become crowded,so the focus of wireless communi-cation has gradually shifted to the underutilized millimeter wave band.In millimeter wave frequency,the main radio frequency chip is divided into two types.One is milli-meter wave communication chip,which mainly uses chips to form phased array to solve the problem of high millimeter wave frequency loss and improve the transmission dis-tance of millimeter wave.The other is millimeter wave radar chip,which uses the char-acteristics of high frequency and good resolution of millimeter wave to realize the de-tection of objects.At the same time,with the increase of frequency,the disadvantage of low integration and high cost of theⅢ-Ⅴgroup process represented by GaAs begin to appear,and the silicon-based process gradually came into people’s view.The imple-mentation method and design technology of silicon based millimeter-wave amplifier chip with high performance and high reliability have become one of the research hotspots.This paper uses 130 nm SiGe process and 28 nm CMOS process to design variable gain amplifier and low noise amplifier respectively.The specific work is as follows:（1）Aiming at the problem that it is difficult to balance the control precision and variable gain range in variable gain amplifier,a novel dB-linear bias-controlled tech-nology is proposed to realize a variable gain amplifier using 130 nm SiGe process.In this technology,the negative feedback resistance is introduced into the current mirror,which enlarges the gain variation range of the amplifier,realizes the dB linear change of the gain,and optimizes the gain variation error of the amplifier.The measured results show that the 1dB bandwidth of the variable gain amplifier covers 16-24 GHz,and the gain range is 15 dB.The minimum RMS gain error of the variable gain amplifier is0.18 dB.The quiescent power consumption of the amplifier is 14 mW,and the core area of the chip is 0.19 mm².The overall performance is internationally leading,achiev-ing small RMS gain error in the gain variation range of 15 dB.（2）Aiming at the problem of high loss and low gain of CMOS process at terahertz frequency,a design method of broadband high gain amplifier combining pole separa-tion of matched network and neutralization capacitor pole modulation are proposed.A low noise amplifier using 28 nm CMOS process are realized.The amplifier adopts the differential transformer coupling circuit structure,and at the same time uses the modu-lation of the gain pole by the change of the neutralization capacitance,combined with the pole separation technology of the matching network,so that the amplifier can form a wide band frequency response.The measured results show that the 3dB bandwidth of the low noise amplifier covers 128-156 GHz,the maximum gain is 19.3dB,the mini-mum simulation noise factor is 7.7 dB,and the simulation IP_1dB is greater than-20 dBm.The power consumption of the circuit is 36 m W,and the core area is 0.08 mm².The overall performance is internationally leading,in the terahertz frequency to achieve 28GHz bandwidth,while achieving high gain.