In the Internet of Things(Io T)application scenario,the Microcontroller Unit(MCU)works in sleep mode most of time,and standby power consumption becomes the key to power optimization.However,the existing Metal-Oxide-Semiconductor Field-Effect Transistor(MOSFET)is difficult to optimize the leakage current continuously.Tunnel field-effect Transistor(TFET)device is an ultra-steep sub-threshold swing device with low leakage current.Integrating TFET in MCU is expected to reduce the overall static power consumption.In this thesis,TFET based circuits and low leakage MCU architecture suitable for TFET device are studied.The key circuits in the always on region of MCU based on TFET devices include digital logic circuit and Static Random Access Memory(SRAM).First,TFET combinational logic cells,TFET-MOSFET hybrid flip-flop circuits and TFET-MOSFET hybrid SRAM are designed.Secondly,the MCU verification platform for deploying TFET devices is constructed,which mainly includes SRAM,Low Dropout Regulator,Real-Time Clock module,Universal Asynchronous Receiver/Transmitter module and Serial Peripherals Interface module.Finally,TFET device is integrated into the always-on region of MCU to replace SRAM,and the simulation was carried out.Using 60 nm silicon based TFET device model,TFET combinational logic cells reduce the static power consumption by 72.07% on average compared with their MOSFET counterparts.And the six hybrid flip-flop circuits can reduce the power delay product by 3.13%~91.3%compared with CMOS circuits.Compared with CMOS SRAM of the same capacity,the singlebit operation energy consumption of TFET-MOSFET hybrid RAM is reduced by 24.4% and the static power consumption is reduced by 78.5%.Using SMIC 55 nm process,the dynamic power consumption of CMOS MCU designed in this thesis is 25.33μA/MHz@3V,and the sleep current is 595 n A@3V.The dynamic power consumption of TFET hybrid integrated MCU is26.1μA/MHz@3V,and the static power consumption is only 323.3n A@3V,which is 45.7%lower than that of CMOS MCU. |