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FPGA Algorithm And Implementation Of Beidou Interface For Multichannel Synchronization

Posted on:2024-05-09Degree:MasterType:Thesis
Country:ChinaCandidate:W G ShiFull Text:PDF
GTID:2568307061966429Subject:Electronic information
Abstract/Summary:PDF Full Text Request
In some areas,such as space launches and weapons range testing,the Time Synchronization System is a very critical component.With the rapid development of modern electronic technology and the continuous improvement of Beidou navigation system in recent years,higher requirements are puting forward for the accuracy,stability and versatility of the time unified system in the field of weapon range testing.In view of these needs,FPGA technology combined with Beidou satellite navigation system is used to study and realize a high-precision,easy-to-carry and high-stability timing system,and the performance of the designed timing system is verified through tests.In this design,the existing timing methods are compared and analyzed,the basic principles of Beidou timing and punctuality technology are studied,the factors affecting punctual accuracy are analyzed and summarized,and the Beidou plus B-code timing method is finally selected.The overall schematic diagram,circuit board design and test results of the instrument are given.This paper focuses on the logical design of the positioning timing system.It mainly includes detailed code design of input module,B-code encoding and decoding module,Beidou B-code priority selection module,synchronization module,time information storage module,delay output module and other modules.Using Verilog language as the logic development language,Quartus II software as a development tool,the above modules are developed,and the problems related to the internal logic of the system are solved.When any signal in the input module is detected,the time information at this time is saved and waits for the delay module to have a time delay instruction,and the accurate time information is output to the external display screen through the output module after the detection is completed.After testing,the positioning function accuracy of the system can reach to 2m,and the punctual accuracy error does not exceed 30 microseconds after 24 hours of loss of timing signal,and the system design is small in size and low in weight.It fully meets the requirements of small size,high precision,multi-function,high reliability,independent and controllable use of the instrument in the photoelectric range test.It also has a wide range of practical application value in the field of space launch.
Keywords/Search Tags:Beidou satellite timing, irig-b code, FPGA, temporal synchronization, temporal delay
PDF Full Text Request
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