Research On RS Encoder And Decoder Based On G 709 And FPGA Implementation

Due to the excellent error control ability,the Reed-Solomon(RS)code is especially suitable for channels with burst errors and random errors,and is widely used in various digital communication systems and digital storage systems.The ITU-G 709 FEC uses an RS(255,239)code.The size of the symbol is 8 bits,and the size of the block,or code word,is255 bytes.There are 239 information symbols per block.16 check symbols are appended to the 239 data symbols,allowing 8 symbol error corrections.The thesis studies the popular Berlekamp-Messay(BM)algorithm.The work of this thesis is divided into encoder and decoder.The main work in encoder is the design of constant coefficient multiplier,which is to improve the performance without affecting the performance of encoder.To solve the low handware efficiency of e Pi BM,a mofidified decoder architecture is proposed.There are a lot of constant coefficient multipliers in RS encoder.From the point of the highest hardware utilization efficiency,a method of multiplier is proposed by adopting the optimization strategy of sharing in whole and two-level XOR.Compared with the traditional design method,it can greatly simplify XOR logic and shorten the critical path.The encoder of the above method designed in this paper is synthesized on Vivado software.Compared with official encoder,it reduces 1.8% look-up table resources and 12% register resources.Look up table and register are the basic FPGA unit of Xilinx.In RS decoder,the existing e PIBM algorithm is analyzed in detail.The me PIBM algorithm is proposed by using the new initial value and correcting the error value formula.Applying the idea of folding,taking the code RS(255239)specified by G 709 as an example,a decoder with folding structure is designed.The decoder effectively solves the problem of low utilization of hardware resources without degrading the decoding performance.The synthesis results show that the hardware area of the decoder designed in this thesis is less than half of decoder of Xilinx.And it is better than most BM algorithm in critical path delay.