Research And Design Of Charge-Pump Phase-Locked Loop

As wireless communication systems bring huge changes and convenience to people’s lives,people’s pursuit of communication technology is also rising.The phase-locked loop is an important part of the wireless transceiver circuit in the communication system.It provides the local oscillator signal for up and down conversion.Its performance determines the communication quality.It is of great significance to design a highperformance phase-locked loop system.This thesis focuses on the design of fast-locking phase-locked loops and voltage-controlled oscillators for special applications.First,the research status of the charge pump phase-locked loop at home and abroad is introduced,and then the main performance indicators of the phase-locked loop are summarized,and the main modules of the phase-locked loop and the noise contributed are analyzed and discussed how to optimize,and then the locking process of the phase-locked loop is introduced.Finally,the basic working theory and noise theory of the voltage controlled oscillator are analyzed and how to optimize the phase noise problem is discussed.Finally,the design of the following modules is completed:1.In view of the trade-off between the phase accuracy of the quadrature oscillator and the phase noise,the high-swing class C and tail harmonic coupling technology are used,and a voltage-controlled oscillator is designed based on the 65 nm CMOS process to realize the quadrature signal output under low phase noise conditions.The power consumption is 15 m W.At 5.75 GHz,the VCO achieves a phase noise of-127 d Bc/Hz at1 MHz offset with a FOM of 190 d Bc/Hz.2.In view of the trade-off between the tuning range and phase noise in the millimeter wave band,a five-fold frequency scheme is adopted.The fundamental oscillator uses a class F structure and tail filtering to generate 2,3 harmonics at the same time,and a mixer is used to generate 5 harmonics.The power consumption is 55 m W,the core power consumption is 20 m W,the tuning range is 33.3GHz～44.3GHz,and the tuning bandwidth is 25.9%.At 38.7GHz,the VCO achieves a phase noise of-108 d Bc/Hz at 1MHz offset.3.On the basis of the current fast-locking technology,a fast-locking phase-locked loop is designed based on the 180 nm CMOS process,two phase thresholds are set,and the current of the charge pump,the width of the waveform,and the order of the filter are switched using a switch.Under the premise of a small bandwidth,the locking time is reduced by 1/3 compared to the traditional phase-locked loop.