Research And Design Of Key Circuit Of Silicon-Based RF Frequency Source

With the rapid development of technology,5G has been extensively applied in our daily life,which results in a large number of intelligent applications.These applications put forward higher requirements to the wireless communication system.The frequency source circuit,being the heart of wireless transceiver,greatly restricts the improvement of the performance of the system.With low cost,low power consumption and high integration,CMOS technology is becoming more and more polupar.But the on-chip passive devices in CMOS technology generally have high loss and low quality factor.The improvement of RF integrated circuit performance mainly depends on two aspects,one is the improvement of the performance of on-chip passive devices,the other is the continuous innovation and optimization of circuit topology,and most of times the latter also comes from the innovation of passive devices.Therefore,this thesis firstly analyzes the working principle and loss mechanism of three kinds of passive devices commonly used,such as inductor,transformer and varactor,and puts forward several optimization methods.In addition,CMOS technology has serious flicker noise.With the decrease of modern CMOS technology node,the frequency of flicker nosie corner of the MOSFETs will even reach rens of MHz.As a result,the VCO’s close-in phase noise is deteriorated.To solve these problems,two kinds of low flicker noise VCO are proposed in this thesis.Firstly,a differential inverse-Class-F VCO based on capacitive coupling is designed using28 nm CMOS technology.This structure inversely couples two identical inverse-class-F VCOs through two coupling capacitors between the gate nodes to achieve differential outputs.The coupling makes the oscillation waveform more symmetrical and reduces the flicker noise upconversion.Then the close-in phase noise of oscillator is optimized.The oscillator core consumes 7.6 m A.And the measured phase noise is-120.5d Bc/Hz@1MHz at 7.5 GHz.The Fo M is 190.7 d Bc/Hz.A noise circulating oscillator based on transformer tri-coupling is designed using 65 nm CMOS technology.In this structure,to avoid the tail current source entering the triode region,two taps from the secondary coil of the transformer are connected to the drain of the tail current source MOSFET.The voltage swing at gate nodes of the cross coupled pairs is increased at the same time.As a result,the phase noise performance of the oscillator is improved.The oscillator core consumes 6.6 m A with the supply voltage of 1V.The measured tuning range is 2.05 GHz～2.43 GHz.And the relative bandwidth is 17%.The phase noise is-133.6 d Bc/Hz@1 MHz at 2.07 GHz.The Fo M is 191.8 d Bc/Hz.In terms of high frequency wideband divider,this thesis also deisgns a current mode logic quart divider using 65 nm CMOS.The tail current source is eliminated to reduce the requirement of power supply voltage.Two bias circuit with enabling function are used at the input of each stage frequency divider.The measurement results show that the frequency divider consumes 4.5 m A with the supply voltage of 1 V.And it can fully cover the VCO ourput frequency range.