Design Of A Charge Pump Circuit For Low Noise And Spur Suppression In A Phase Locked Loop

With the advent of 5G communication,wireless communication has been unprecedentedly concerned.To keep the communication in good quality at the corresponding frequency,the design of millimeter-wave frequency synthesizers with low phase noise and low spur has become a major challenge in the field of wireless communication.Charge pump phase-locked loop has become one of the most popular architectures as a frequency synthesizer due to its superior frequency acquisition and tracking abilities.Charge pump plays the role of the key digital-to-analog conversion module in the charge pump phase-locked loop,whose output current noise becomes the main contributor within the loop bandwidth,and its current mismatch and non-ideal effect worsens the reference spur of the loop.Therefore,it is essential to bring up a charge pump circuit for low noise and spur suppression phase-locked loop at high operating frequency.This thesis analyzes the noise source and the transfer of the charge pump output current,as well as charge pump’s contribution of output spur.After that,a charge pump circuit structure with low output noise and spur contribution is proposed.This circuit takes advantages of a novel high-impedance current mirror and the feedback regulation by an error amplifier to achieve ultra-low current mismatch without sacrificing too much output swing.Also,this circuit utilizes a current steering technology for fast switching speed.The proposed charge pump circuit is implemented in 65 nm CMOS process with1.2V power supply.The simulation results show that the charge pump circuit consumes0.87 m W,and it is able to achieve 0.46% current mismatch and 4.2% current variation within the output voltage dynamic range of 0.2V-1V.The output current noise @1KHz is-223.5d B/Hz,while the output current noise @1MHz is-235.1d B/Hz.