Research On Time-Domain Based Intelligent Edge Processing Core With Non-Volatile Memory

In recent years,with the rapid development of artificial intelligence algorithms,the deployment of artificial intelligence algorithms to edge-side devices has become a research hotspot.However,most edge-side devices are powered by batteries and are sensitive to power consumption.The neural network has a large number of parameters,requiring a large amount of memory for data storage,as well as a large amount of on-chip and off-chip data movement.The traditional Von Neumann structure has serious problems of memory wall and power wall in the edge-side equipment.In response to the above problems,this thesis proposes an edge-side time-domain intelligent processing core based on non-volatile memory,which uses block power gating and resistive memory with gated clock to reduce storage power consumption when idle.In terms of computing,this thesis proposes a time-domain computing method to reduce computing power consumption,and uses a customized SRAM array combined with in-memory computing to further alleviate the storage wall problem.The main work of this thesis is divided into the following three parts:First of all,this thesis analyzes the neural network deployment problems faced by edge-side devices,and discusses the current domestic and foreign development status of resistive memory,in-memory computing,and time domain computing.At the same time,this thesis compares and analyzes the advantages and disadvantages of traditional digital domain,analog domain and time domain computing.And designed a high-precision timedomain calculation method and time-domain calculation circuit unit,and customized a9T-SRAM unit and a time-domain in-memory calculation circuit,which can support highprecision time-domain MAC(Multiply-Accumulate)operations.Secondly,on the basis of in-memory computing and time-domain computing circuits,an in-memory computing array based on time domain is designed.The computing array can reduce the transistor turnover and data transfer of the computing circuit,thereby reducing the computing and transfer power consumption brought by the neural network inference.Next,in order to store a large number of parameters required for neural network inference at the edge,this thesis designs RRAM with block clock and power gating.The memory is divided into multiple memory blocks,and different memory blocks can be clocked or power gated independently.During the inference process,only one of the blocks needs to be turned on for parameter reading,and the other blocks enter the power gating or clock gating state,thereby reducing power consumption during storage.Finally,this thesis uses the front-end and back-end design process of integrated circuits to verify the above technologies and analyze the power consumption.The CSMC250 nm technology is used to customize the design of the time-domain in-memory computing circuit,and realize the layout design and tape-out.In terms of resistive variable memory,TSMC 22 nm is used to realize the chip design and tape-out verification of largecapacity resistive variable memory,which proves the function of fine-grained gating proposed in this thesis.And adopt TSMC 22 nm technology to realize the analysis of related control circuit and calculation circuit.It is proved that the power consumption of the time domain computing circuit in the working state is reduced by 2.5 times compared with the digital domain,and the power consumption of the resistive variable memory is one-twelfth of that of the static random access memory.Finally,we implemented the ECG intelligent processor by using the time-domain in-memory computing circuit technology and the resistive variable memory to conduct a complete power consumption analysis.Its power consumption of 6.8μW under continuous operation is lower than other advanced works,which proves that the design has certain advantages in edge scenarios.