Design And Implementation Of Back-end For Ethernet Chip Based On PCIe Interface

Since its introduction,Ethernet technology has been providing technical standards and specifications for high-speed and stable data transmission,and it has also become the most common Internet technology today.With the rapid development of the IC industry,the demand for Ethernet chips based on Ethernet technology has been increasing,and Ethernet chips are now widely used in important fields such as automotive electronics,consumer electronics,and information and communication.The Ethernet chip based on PCIe interface designed in this thesis can be compatible with both PCIe interface and Ethernet protocol,where Ethernet conforms to IEEE 802.3standard Ethernet format and PCIe conforms to PCIe 1.1 specification.The Ethernet chip also includes GMII three-speed interface and supports remote wake-up function.Based on 130 nm CMOS process,this thesis completes all back-end design process of this Ethernet chip from netlist to physical verification.The main research work of the thesis is as follows:Firstly,a brief introduction to the current research status of Ethernet chip and PCIe interface,a study and description of PCIe interface and Ethernet protocol,and an analysis and theoretical introduction to the low-power methods and timing optimization methods commonly used in digital back-end design.Then,based on the existing process library of this design,two low-power methods and two timing optimization methods are introduced and implemented respectively based on the characteristics of this design,namely,multi-threshold voltage technique,gated clock technique to reduce chip power consumption and Path Group,Useful Skew to optimize chip timing.In this thesis,the multi-threshold voltage technique is improved on the basis of the traditional implementation method to obtain a more significant power gain,and the gated clock technique is analyzed and investigated the effect of different parameters on power consumption to obtain a more suitable gated clock insertion scheme for this design and lower total chip power consumption.The useful skew method yields a lower WNS.The thesis then describes in detail the back-end implementation process of the chip from Floorplan to Routing and performs data output.Finally,static timing analysis and timing repair,physical verification work are completed according to the output results,and finally the chip was successfully taped out.