Machine Learning-aided PBA Timing Prediction And Automated Optimization Methods

In the past few decades,integrated circuits have developed in accordance with Moore’s Law.The feature size of chips has continued to shrink,the number of transistors has reached tens of billions,and the complexity of chip design,integration difficulty,and design costs have continued to increase.Physical design occupies most of the chip design time,and the process requires a huge amount of calculation and intensive algorithm support.Therefore,most physical design processes rely on electronic design automation(EDA)tools to complete.In order to overcome the challenges in modern physical design,EDA suppliers began to introduce artificial intelligence(AI)and machine learning(ML)technologies into their products,trying to shorten the physical design process time and reduce design costs.The application of machine learning in physical design implementation has the following points:(i)Eliminate unnecessary design and modeling margins;(ii)Use downstream process result prediction to achieve faster design convergence;(iii)Optimize resource allocation.The physical design assisted by machine learning can greatly improve the performance,power consumption and area indicators of the chip,improve engineering efficiency,and ultimately shorten the time to market for the chip.Static timing analysis is a very important timing check technique in the physical design process of integrated circuits.It determines whether the chip can work normally at the required frequency.Under the advanced technology node,the trade-off between timing analysis speed and accuracy has become a huge difficulty.Path-based analysis(PBA)mode in commercial tools is expensive and time-consuming,which forces designers to adopt faster graph-based analysis(GBA)mode,but at the cost of pessimism.The use of machine learning technology can realize the prediction from GBA timing results to PBA timing results to achieve the purpose of reducing pessimism.However,there is a problem of asymmetry in the prediction risk loss during the prediction process,that is,relative pessimism has less impact than relative optimism.After timing analysis,it is necessary to optimize and repair the timing violation path.Engineering command order(ECO)is the main method of timing optimization.Timing ECO is a step that requires a lot of engineer experience and manual operation,and requires multiple process loop iterations.Repairing all illegal paths is time-consuming and labor-intensive.The main research content of this paper is to establish a machine learning-assisted timing prediction and optimization model,accelerate the chip timing analysis process,and reduce the loss of chip performance,power consumption and area(PPA)caused by over-design.The main research content and related innovations of this article are as follows:(i)The advantages and disadvantages of different methods of calculating path delay are compared and analyzed,and a method of path delay prediction based on the gate-wire delay model composed of "gate + wire" in PBA timing prediction and ECO timing optimization tasks is proposed.This method is convenient to extract features.It can adapt to arbitrarily complex paths and effectively capture the internal state of the path,and quickly calculate the advantages of path delay.(ii)One of the research contents of this paper is to implement a stage delay prediction model based on custom loss function technology to quickly generate PBA timing results from pessimistic GBA results.The model can also identify false violation paths in the GBA timing report,and can reduce over-design and chip PPA loss caused by timing repair in the timing optimization stage.The experimental results show that for the design of millions of logic gates in 28 nm process,the average absolute error of the predicted PBA timing slack at each corner is reduced by 66.7%～79.8% compared with the real GBA-PBA timing slack error(from 17.79 ps to 5.92 ps and 3.6ps),saving 300 times the runtime overhead.It can correct approximately 75.6% of false violation paths in the GBA timing report.(iii)The second research content of this paper is to propose a machine learning-aided ECO path delay prediction model and an automated ECO optimization flow.By establishing a stage delay model to provide a more accurate estimate of path delay,the prediction error is 1.26 ps at 48623 stages.The mean absolute error of the predicted 2780 path delays is 2.61 ps.Among them,the average relative percentage error on 435 ECO test paths is only 0.47%.The automated ECO algorithm is realized by replacing the threshold voltage and channel length of the drive cell,and the average optimization rate of the path delay on the hold time violation paths is 91.5%.The automated ECO process assisted by machine learning is used to assist the manual repair of the violation timing path,which can effectively reduce the number of iterations of timing ECO and the complexity of manual repair and timing evaluation,greatly reducing the timing optimization time,and has considerable application value.