Design Of A 9-bit Second-order Noise Shaping Successive Approximation Analog-to-Digital Converter

Analog to Digital Converter(ADC)is an essential module in many fields,such as wireless communication,industrial control,and medical electronics.In CMOS image sensors,ADC is the core module,and its performance such as speed,accuracy,and power consumption are the main factors that restrict the performance of image sensors.There are many types of ADC,among which the Successive Approximation Register(SAR)ADC and Sigma Delta ADC are two classic structures,each with its own advantages and disadvantages.Noise Shaping(NS)SAR ADC,which combines the advantages of two types of ADC,can achieve medium speed and high accuracy at lower power consumption,which is beneficial for improving the performance of image sensors.In this thesis,structural improvements and optimizations have been made to overcome the shortcomings of conventional passive integrators and multi input comparators with high input reference noise.A new type of passive integrator has been adopted,which can not only achieve the function of sampling and integrating residual voltage,but also achieve amplification of the integration signal to compensate for the attenuation coefficient;Aiming at the problem that the capacitance mismatch error in ADC is not integer by the system,resulting in a decrease in accuracy,this thesis introduces the Data Weight Average(DWA)technology to effectively suppress harmonics caused by capacitance mismatch;At the same time,a new second-order noise shaping loop is also adopted,effectively reducing the noise shaping operations in one cycle of the system,further improving the speed of the system.Finally,this thesis designs a noise shaping SAR ADC based on the 130 nm BCD process,and carries out circuit design and simulation verification.The design has a power supply voltage of 1.5V,a sampling frequency of 1MS/s,an oversampling rate of 8,and a capacitance DAC of 9 bits.At an input signal frequency of 62 KHz,the simulation results show that SFDR is 98.24 d B,SNDR is 86.75 d B,ENOB is 14.12 bits,and power consumption is 559.52 μ W.The simulation results achieve the expected goals.