Design And Implementation Of A Digital On-chip Calibration Technique For Nonlinearity Error Of Pipelined-SAR ADC

The Analog to Digital Converter(ADC),which is a high-speed,high-precision,and low-power interface tool,is a core device for digital processing of natural information.With the continuous increase of national defense security requirements and consumer electronic device performance demands,the speed and power consumption of ADCs face increasingly higher requirements.Consequently,a series of mixed ADCs have been developed,such as Pipelined Successive Approximation Register(Pipelined-SAR)ADC,which has been widely studied due to its high speed and low power consumption.Thesis focuses on the digital calibration technology for non-linear errors of Pipelined-SAR ADC.The main research contents and achievements are presented as follows:(1)Based on the working principles and error sources of Pipelined-SAR ADC,thesis determines the types of digital calibration for errors,which mainly includes calibrations for inter-stage gain non-linearity,comparator offset,and capacitor mismatch errors.Subsequently,a workload quantization model for Pipelined-SAR ADC and its corresponding error source model are established,and an overall calibration scheme for Pipelined-SAR ADC is proposed.(2)To address the inter-stage gain non-linearity error in Pipelined-SAR ADC,thesis proposes a method that directly uses calibration functions for error correction,including function selection and specific point extraction.The inter-stage gain non-linearity error is transformed into calibration function coefficients by restoring it and calculating the coefficients.The specific point extraction is based on statistical regularities and the characteristics of the residual transfer function curve of Pipelined-SAR ADC,where specific points are extracted from a certain sample space and averaged to reduce errors and improve the accuracy of the calibration coefficients.The specific point extraction is also used for the calibration of comparator offset and capacitor mismatch errors.(3)Building upon the inter-stage gain calibration,thesis combines specific points and the characteristics of comparator offset to calculate the specific value of offset and compensate it on the output code of the Pipelined-SAR ADC.The calibration of capacitor mismatch is based on the relationship between the entry into the sub-harmonic state of the comparator and the size of the capacitor mismatch.It is then applied to the calibration of Pipelined-SAR ADC,and finally,the output code is synthesized to Vout according to the weights,and the calibration process is completed.The digital calibration algorithm proposed in this thesis is validated through simulation on a 14-bit 500MS/s Pipelined-SAR ADC model.Initially,Python simulations are employed to demonstrate the capability of the proposed calibration algorithm in correctly calibrating the corresponding error sources and to establish the algorithm’s robustness.Subsequently,RTL-level design is carried out using Vivado software,followed by functional simulation verification.After applying the calibration algorithm to the digital logic circuit,significant improvement was observed in the performance of the ADC.The signal-to-noise distortion ratio increased from 58.81 d B to 79.93 d B,effective number of bits increased from 9.48 bits to 12.96 bits,and spurious-free dynamic range increased from 71.75 d B to 97.48 d B.These results collectively demonstrate the efficacy of the calibration algorithm in enhancing the overall performance of the ADC.